Chip size package and method of manufacturing the same

Details Chip size package and method of manufacturing the same Chip size package and method of manufacturing the same

1998-03-26

1999-09-07

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257783, 257789, 257793, 257703, H01L 2348, H01L 2352, H01L 2940

Patent

active

059491426

ABSTRACT:
A chip size package is constituted by a chip on which an integrated circuit is formed, and plated bumps are formed at terminal portions of the integrated circuit, a flexible two-layered printed-circuit board having interlevel conductive bumps for electrically connecting metal patterns formed on the two surfaces of the flexible board, and an anisotropic conductive film for electrically connecting the plated bumps arranged on the chip to the flexible two-layered printed-circuit board, and fixing the chip onto the flexible two-layered printed-circuit board. With these features, the chip size package is excellent in mass production without any sealing by potting and any setting/removing on/from a convey jig and the like for every product.

REFERENCES:
patent: 5468655 (1995-11-01), Greer
patent: 5610442 (1997-03-01), Schneider et al.
patent: 5729440 (1998-03-01), Jimarez et al.
patent: 5763295 (1998-06-01), Tokumo et al.
patent: 5864178 (1999-01-01), Yamada et al.

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