Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-06-22
2003-03-04
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S455000, C438S459000
Reexamination Certificate
active
06528344
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip scale surface-mountable packaging method for electronic and micro-electro mechanical system (MEMS) devices.
2. Description of the Related Art
A conventional wafer level chip scale package will be described with reference to FIG.
1
. As shown in
FIG. 1
, an active region
4
in which a large number of integrated circuits are formed is located in a first substrate
1
. A second substrate
2
serving as a cover for protecting the active region
4
is combined with the first substrate
1
while being supported by a frit glass wall
3
. An external interconnect electrode
5
is arranged on the first substrate
1
but does not extend up to the surface of the second substrate
2
. To install this type of chip package into a system for use, wire bonding is necessary. When a chip package is fabricated such that the capillary of a wire bonder does not reach the second substrate
2
, there is a problem in that the size of individual chips increases. In addition, a flip chip bonding technique, which is widely used in surface mount packaging applied for the purpose of manufacturing miniature chips, cannot be applied to such a conventional package structure.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is an object of the present invention to provide a method for fabricating a new chip scale surface-mountable package for a variety of electronic or micro-electro mechanical system (MEMS) devices, in which both electric and physical passivation and interconnection with external circuits can be achieved at a wafer level.
To achieve the object of the present invention, there is provided a chip scale surface-mountable packaging method for electronic and MEMS devices, comprising: (a) forming an interconnection and sealing pattern as a deep trench in one surface of a conductive cover substrate using semiconductor fabricating and micromachining techniques; (b) filling the trench as the pattern of the cover substrate with an insulating material such as glass or ceramic and planarizing the surface of the cover to form a bonding pattern; (c) accurately aligning the cover substrate with a device substrate, in which electronic or MEMS devices are integrated, and bonding the cover substrate and the device substrate; (d) polishing the other surface of the cover substrate and forming an electrode pattern thereon; and (e) dicing the sealed and interconnected substrates to form a complete chip scale package.
It is preferable that the cover substrate is formed as an impurity-doped conductive semiconductor substrate or a metal substrate having a processing suitability and a melting point higher than a predetermined temperature. It is preferable that, in step (a) of forming the interconnection and sealing pattern in the cover substrate, the deep trench has a depth of hundreds of micrometers.
It is preferable that the semiconductor substrate is formed of silicon (Si), and the metal substrate is formed of a metal selected from the group consisting of stainless steel, Kovar, and copper (Cu).
It is preferable that, in filling the trench of the cover substrate with ceramic in step (b), ceramic paste is coated on the surface of the cover substrate and packed into the trench of the cover substrate under pressure, and the resultant cover substrate is thermally processed in a furnace. It is preferable that planarizing the cover substrate in step (b) is performed using chemical mechanical polishing (CMP) to minimize surface roughness of the cover substrate and to expose the interconnection and bonding patterns of the cover substrate. It is preferable that step (c) is performed by a bonding method selected from the group consisting of solder bonding, eutectic bonding, zero gap bonding, anisotropic conductive film bonding, conductive epoxy bonding, and anodic bonding.
REFERENCES:
patent: 5605489 (1997-02-01), Gale et al.
patent: 5637539 (1997-06-01), Hofmann et al.
patent: 5907768 (1999-05-01), Malta et al.
patent: 5919548 (1999-07-01), Barron et al.
patent: 6136243 (2000-10-01), Mehregany et al.
patent: 6297072 (2001-10-01), Tilmans et al.
Burns Doane , Swecker, Mathis LLP
Cuneo Kamand
Geyer Scott
Samsung Electronics Co,. Ltd.
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