Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2007-05-01
2007-05-01
Lee, Calvin (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C438S368000
Reexamination Certificate
active
11082080
ABSTRACT:
A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.
REFERENCES:
patent: 3698080 (1972-10-01), Berner
patent: 4249299 (1981-02-01), Stephens et al.
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5324981 (1994-06-01), Koboki et al.
patent: 5338967 (1994-08-01), Kosaki
patent: 5597767 (1997-01-01), Mignardi et al.
patent: 5753529 (1998-05-01), Chang et al.
patent: 5757081 (1998-05-01), Chang et al.
patent: 5767578 (1998-06-01), Chang et al.
patent: 5872396 (1999-02-01), Kosaki
patent: 5888884 (1999-03-01), Wojnarowski
patent: 5910687 (1999-06-01), Chen et al.
patent: 6054760 (2000-04-01), Martinez-Tovar et al.
patent: 6242283 (2001-06-01), Lo et al.
patent: 30 09 985 (1981-09-01), None
patent: 07 169796 (1995-07-01), None
patent: WO98/19337 (1998-05-01), None
Lawrence Kren, “The Race For Less Space”, Machine Design, Jul. 8, 1999, pp. 86-89.
Patrick Mannion, “MOSFET's Break Out Of The Shackles Of Wirebonding”, Electronic Design, Mar. 22, 1999, vol. 47, No. 6, pp. 1-5.
Ho Yueh-Se
Kasem Y. Mohammed
Zandman Felix
Lee Calvin
Vishay-Siliconix
LandOfFree
Chip scale surface mount package for semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chip scale surface mount package for semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale surface mount package for semiconductor device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3764249