Chip scale surface mount package for semiconductor device...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S622000, C257S625000, C257S723000, C257S730000, C257S692000, C257S698000, C257S690000

Reexamination Certificate

active

06876061

ABSTRACT:
A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.

REFERENCES:
patent: 4249299 (1981-02-01), Stephens et al.
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5324981 (1994-06-01), Koboki et al.
patent: 5338967 (1994-08-01), Kosaki
patent: 5753529 (1998-05-01), Chang et al.
patent: 5757081 (1998-05-01), Chang et al.
patent: 5767578 (1998-06-01), Chang et al.
patent: 5872396 (1999-02-01), Kosaki
patent: 5888884 (1999-03-01), Wojnarowski
patent: 5910687 (1999-06-01), Chen et al.
patent: 6054760 (2000-04-01), Martinez-Tovar et al.
patent: 07169796 (1995-07-01), None
patent: WO 9819337 (1998-05-01), None
Lawrence Kren, “The Race For Less Space”, Machine Design, Jul. 8, 1999, pp. 86-89.
Patrick Mannion, “MOSFETs Break Out Of The Shackles Of Wirebonding”, Electronic Design, Mar. 22, 1999, vol. 47, No. 6, pp. 1-5.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Chip scale surface mount package for semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip scale surface mount package for semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale surface mount package for semiconductor device... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3379409

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.