Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-12-08
2002-08-27
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S686000, C257S690000, C257S710000
Reexamination Certificate
active
06441475
ABSTRACT:
BACKGROUND OF THE INVENTION
After the processing of a semiconductor wafer has been completed, the resulting integrated circuit (IC) chips or dice must be separated and packaged in such a way that they can be connected to external circuitry. There are many known packaging techniques. Most involve mounting the die on a leadframe, connecting the die pads to the leadframe by wire-bonding or otherwise, and then encapsulating the die and wire bonds in a plastic capsule, with the leadframe left protruding from the capsule. The encapsulation is often done by injection-molding. The leadframe is then trimmed to remove the tie bars that hold it together, and the leads are bent in such a way that the package can be mounted on a flat surface, typically a printed circuit board (PCB).
This is generally an expensive, time-consuming process, and the resulting semiconductor package is considerably larger than the die itself, using up an undue amount of scarce “real estate” on the PCB. In addition, wire bonds are fragile and introduce a considerable resistance between the die pads and the leads of the package.
The problems are particularly difficult when the device to be packaged is a “vertical” device, having terminals on opposite faces of the die. For example, a power MOSFET typically has its source and gate terminals on the front side of the die and its drain terminal on the back side of the die. Similarly, a vertical diode has its anode terminal on one face of the die and its cathode terminal on the opposite face of the die. Bipolar transistors, junction field effect transistors (JFETs), and various types of integrated circuits (ICs) can also be fabricated in a “vertical” configuration.
Accordingly, there is a need for a process which is simpler and less expensive than existing processes and which produces a package that is essentially the same size as the die. There is a particular need for such a process and package that can be used with semiconductor dice having terminals on both their front and back sides.
SUMMARY OF THE INVENTION
These objectives are achieved in a semiconductor package fabricated in accordance with this invention. The fabrication process starts with a semiconductor wafer including a plurality of dice and includes: forming an overcoat on a surface of the wafer; attaching the wafer to a substrate; patterning the overcoat to expose connection pads on a front side of the dice; forming an electrically conductive wraparound layer on a side of a die, the wraparound layer wrapping around an edge of the die to form at least a portion of an electrical connection between a location on the front side of the die and a terminal on a back side of the die; and breaking the wafer into individual dice.
In one version of the process, the formation of a wraparound layer includes severing the wafer along parallel lines between the dice so as to yield a plurality of multiple-die strips; mounting the strips adjacent to each other, sandwich-like, to form a stack; depositing at least a first metal layer on an exposed side of the stack, the first metal layer wrapping around the edge of each die to form an electrical connection between the front side of the die and an electrical terminal on the back side of the die; disassembling the strips in the stack; separating the individual dice in the strips; and plating a second metal layer over the first metal layer. The first and second metal layers are, in effect, sublayers of a single metal “layer”.
The process may include forming a solderable metal layer on the connection pads. The solderable metal layer can be formed, for example, by removing a native oxide layer from the connection pad (e.g., removing aluminum oxide from an aluminum layer) and depositing a solderable metal such as gold, nickel or silver on the exposed metal by sputtering or plating.
The process may also include forming solder or polymer bumps or balls on the connection pads on the front side of the die, thereby enabling the package to be mounted to a PCB using known flip-chip techniques.
In some embodiments, perpendicular saw cuts are made between the dice, the cuts extending partially through the substrate such that the substrate remains intact at its back side. The multiple-die strips are formed by breaking the wafer along a series of parallel cuts. After the first metal layer has been deposited and the stack has been disassembled, the strips are broken into individual dice along the cuts perpendicular to those that were broken to form the strips.
The substrate may be a sheet of a conductive material such as copper or aluminum and may be attached to at least one terminal on a back side of the die with a conductive cement. The conductive substrate may serve as a heat sink as well as an electrical contact. Alternatively, the substrate may be nonconductive, and vias or holes may be formed in the substrate and filled with a conductive material to facilitate electrical contact with the back side of the die.
Typically the first metal layer is a relatively thin layer deposited by sputtering or evaporation and the second metal layer is a relatively thick layer formed by plating. In some embodiments, it may be possible to make the first metal layer thick enough that the second metal layer can be omitted.
In some cases, it may be desirable to make the semiconductor wafer thinner, for example by grinding the back side of the wafer, to reduce the resistance of the semiconductor device. To provide support for the wafer during grinding, the front side of the wafer is initially attached to a supporting substrate, which could be made of a nonconductive material such as glass or a conductive material such as copper. Holes are opened in the supporting substrate to expose the connection pads on the front side of the wafer.
A semiconductor package in accordance with this invention comprises a semiconductor die; a supporting substrate attached to a back side of the die; a nonconductive overcoat overlying a front side of the die, an opening in the overcoat corresponding with a connection pad on the front side of the die, and an electrically conductive wraparound layer (which may include a conductive polymer layer or one or more metal layers or sublayers) extending from the front side of the die, around an edge of the die to the substrate, and thereby establishing an electrical connection between a location on the front side of the die and a terminal on the back side of the die. A solder or polymer bump or ball can be formed on the connection pad.
In one embodiment, the semiconductor package includes a vertical power MOSFET, and the supporting substrate comprises a sheet of copper. The overcoat is patterned so as to expose source and gate pads on the front side of the die. The copper substrate is attached with a conductive cement to a drain terminal on the back side of the die, and the wraparound layer extends around an edge of the die to establish an electrical connection between the front side of the die and the copper substrate. The portion of the wraparound layer on the front side of the die effectively forms a front side drain pad. Solder balls are formed on the source, gate and drain pads. The package can be inverted and mounted, flip-chip style, on a PCB.
In another embodiment, the substrate is nonconductive, and vias filled with a conductive material extend through the substrate to allow electrical contact between the wraparound layer and the terminal on the back side of the die.
Semiconductor packages according to this invention do not require an epoxy capsule or bond wires; the one or more substrates attached to the die serve to protect the die and act as heat sinks for the die; the packages are very small (e.g., 50% the size of molded packages) and thin; they provide a very low on-resistance for the semiconductor device, particularly if the wafer is ground thinner; they are economical to produce, since they require no molds or lead frames; and they can be used for a wide variety of semiconductor devices such as diodes, MOSFETs, JFETs, bipolar transistors and various types of integrated circ
Ho Yueh-Se
Kasem Y. Mohammed
Zandman Felix
Flynn Nathan
Forde Remmon R.
Skjerven Morrill LLP
Vishay Intertechnology Inc.
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