Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
1999-10-20
2002-10-08
Vu, Bao Q. (Department: 2838)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S692000, C257S780000
Reexamination Certificate
active
06462274
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates, in general, to chip-scale semiconductor packages and a method of manufacturing such packages and, more particularly, to a chip-scale semiconductor package of the fan-out type and a method of manufacturing such a package, with solder balls of the package being arranged on an external area of a circuit substrate extending outside the edge of a semiconductor chip in addition to the area of the substrate above the chip, the package thus carrying an increased number of solder balls, or the signal input/output terminals, thereon.
DESCRIPTION OF THE PRIOR ART
As is well known to those skilled in the art, a semiconductor package is a device designed to mount a semiconductor chip on a mother board, in addition to intermediating input/output signals between the chip and the mother board. In accordance with the recent trend of compactness, lightness, thinness and smallness of semiconductor chips, it has been necessary to make such semiconductor packages of a chip size meeting the compactness, lightness, thinness and smallness of the semiconductor chip. Such a chip-sized package is so-called a chip-scale semiconductor package in the art.
FIGS. 11 and 12
show the construction of two types of conventional chip-scale semiconductor packages, respectively.
The package
100
′ of
FIG. 11
is a conventional chip-scale package of the lead type. As shown in the drawing, the chip-scale package
100
′ of the lead type comprises a semiconductor chip
40
′, having a plurality of signal input/output pads
41
′ on its opposite upper edges or along the square edge. Such pads
41
′ are called “edge pads” in the art. A flexible circuit substrate
10
′ is attached to the upper surface of the chip
40
′ by an adhesive layer
21
′, except for an area around the signal input/output pads
41
′, with the adhesive layer
21
′ being uniformly formed between the substrate
10
′ and the chip
40
within an area of the substrate
10
′. The above substrate
10
′ has a plurality of integrated circuit patterns regularly arranged on its polyimide layer
12
′. The above circuit patterns, individually comprising a lead
13
′, a connector
14
′ and a solder ball land
15
′, are electrically connected to the signal input/output pads
41
′ of the chip
40
′ at the leads
13
′, respectively. A cover coat
16
′ is coated on the top surface of the substrate
10
′ in a way such that the coat
16
′ opens for both the leads
13
′ and the solder ball lands
15
′ of the circuit patterns. A solder ball
70
′ is welded to each of the solder ball lands
15
′ which are exposed through the cover coat
16
′. The solder balls
70
′ are used for mounting the semiconductor package
100
′ on a mother board and as signal input/output terminals of the package
100
′. In order to protect both the pads
41
′ of the chip
40
′ and the leads
13
′ of the circuit patterns from the atmospheric environment, the opposite upper edges or the square upper edge of the chip
40
′ are individually covered using a packaging material, thus forming a packaging part
60
′.
On the other hand, the package
101
′ of
FIG. 12
is a conventional chip-scale package of the wire type. As shown in the drawing, the general shape of the chip-scale package
101
′ of the wire type remains the same as that described for the lead-type package
100
′, but the circuit patterns of the substrate
10
′ of this package
101
′ do not have leads
13
like the package
100
′, and are electrically connected to the signal input/output pads
41
′ of the chip
40
′ using a-plurality of bonding wires
50
′ in place of the leads
13
′. Further explanation for the-wire-type package
101
′ is thus not deemed necessary.
In the above-mentioned packages
100
′ and
101
′, the signal input/output terminals, or the solder balls
70
, are only arranged on a limited area above the top surface of the chip
40
′. That is, the solder ball area of each of the packages
100
′ and
101
′ is limited, and so such a package
100
′,
101
′ is called a package of the “fan-in” type in the art. Therefore, such a chip-scale package
100
′,
101
′ of the fan-in type fails to effectively meet the recent trends of compactness and smallness of the semiconductor packages or of a remarkable increase in the number of signal input/output terminals of packages. That is, since the solder ball area of the package of the fan-in type is limited, it is almost impossible for such a package to carry a desired number of solder balls within the limited solder ball area. This finally limits the designing flexibility of the chip-scale semiconductor packages.
In an effort to solve the above-mentioned problem, the outside edge of the substrate
10
′ may be designed to further extend outwardly until the substrate
10
′ exceeds the edge of the chip
40
, thus forming an exterior area for carrying additional solder balls
70
′ thereon. However, since a flexible substrate
10
′ is used in the conventional packages
100
′ and
101
′ as described above, such an exterior area of the substrate
10
′, exceeding the edge of the chip
40
′, may be bent downwardly. In such a case, it is almost impossible to weld any solder ball
70
′ to a solder ball land
15
′ provided on the exterior area of the substrate
10
′. Even if a solder ball
70
′ is welded to a solder ball land
15
′ on such an exterior area of the substrate
10
′ with difficulty, the solder balls
70
′ of a package
100
′,
101
′ may fail to accomplish a desired horizontally since the flexible substrate
10
is bent at said exterior area.
In the chip-scale package
100
′ of the lead type shown in
FIG. 11
, the leads of the circuit substrate are directly bonded to the signal input/output pads or the edge pads of the semiconductor chip through a tape automated bonding process. However, an excessive bonding force is applied to the semiconductor chip during such a tape automated bonding process, thus sometimes damaging or breaking the chip. In addition, the leads of the substrate of the above package
100
′ are designed to be thick and wide. Such thick and wide leads regrettably limit the designing flexibility of the remaining parts of the circuit patterns, or the connectors
14
′ and the solder ball lands
15
′, of the packages
100
′.
The above-mentioned semiconductor packages
100
′ and
101
′ may be produced as follows. In order to produce such a package
100
′,
101
′, a wafer-shaped circuit substrate is primarily prepared. Thereafter, the wafer-shaped substrate is attached to a wafer, having a plurality of semiconductor chip units, using an-adhesive layer. This step is so-called a wafer lamination step in the art. After the wafer lamination step is accomplished, a wire/lead bonding step is performed. In the wire/lead bonding step, each signal input/output pad of each of the semiconductor chip units of the wafer is electrically connected to an associated bond finger of the substrate through a bonding process using a lead or a wire. The lead/wire bonding step is followed by a packaging step wherein the opposite upper edges or a square upper edge of each of the semiconductor chip units are individually packaged with a packaging part. The objective of the above packaging part is to protect the lead/wire bonding part, comprising the signal input/output pads and the leads or wires, from the atmospheric environment. Thereafter, a solder ball welding step, wherein a plurality of solder balls, or the signal input/output terminals of a package, are welded to the solder ball lands of the substrate, is performed. A singulation step follows the solder ball w
DiCaprio Vincent
Han Byung Joon
Hoffman Paul
Park Chang Kyu
Shim Il Kwon
Amkor Technology Inc.
Laxton Gary L.
Vu Bao Q.
LandOfFree
Chip-scale semiconductor package of the fan-out type and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chip-scale semiconductor package of the fan-out type and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip-scale semiconductor package of the fan-out type and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2926276