Chip scale pin array

Details Chip scale pin array Chip scale pin array

2000-10-26

2004-02-10

Talbott, David L. (Department: 2827)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S123000, C438S124000, C257S666000, C257S676000

Reexamination Certificate

active

06689640

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit packages. More specifically, the invention relates to chip scale integrated circuit packages.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) package encapsulates an IC chip (die) in a protective casing and may also provide power and signal distribution between the IC chip and an external printed circuit board (PCB). An IC package may use a metal lead frame to provide electrical paths for that distribution.
To facilitate discussion,
FIG. 1
is a top view of a lead frame panel
100
made up for a plurality of lead frames that may be used in the prior art. The lead frame may comprise leads
108
, die attach pads
112
, ties
116
for supporting the die attach pads
112
, and a skirt
120
for supporting the plurality of leads
108
and ties
116
. The lead frame panel
100
may be etched or stamped from a thin sheet of metal. IC chips
124
may be mounted to the die attach pads
112
by an adhesive epoxy. Wire bonds
128
, typically of fine gold wire, may then be added to electrically connect the IC chips
124
to the leads
108
. Each IC chip
124
may then be encapsulated with part of the leads
108
and the die attach pad
112
in a protective casing, which may be produced by installing a preformed plastic or ceramic housing around each IC chip or by dispensing and molding a layer of encapsulating material over all IC chips
124
.
FIG. 2
is a cross-sectional view of part of the lead frame panel
100
and IC chips
124
. In a process described in U.S. patent application Ser. No. 09/054,422, entitled “Lead Frame Chip Scale Package”, by Shahram Mostafazadeh et al., filed Apr. 2, 1998, a tape
136
is placed across the bottom of the lead frame panel
100
and an encapsulating process is used to encapsulate the IC chips
124
, the wire bonds
128
, and part of the lead frame panel
100
. The tape
136
prevents the encapsulating material
140
from passing through the lead frame panel
100
. Once the encapsulating material
140
is hardened, the tape
136
may be removed. The encapsulating material
140
may be cut to singulate the IC chips
124
and leads
108
. The resulting singulated IC chips have leads with a length
155
which is substantially parallel to the conductive surface of the IC chips
124
.
It is desirable to provide an IC package process which does not require the steps of creating wire bonds between the die and leads, adding tape to the lead frame, and then removing the tape from the lead frame. It is also desirable to provide a process and lead frame that provides lead fingers and a chip scale footprint.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, the invention provides an integrated circuit package. The integrated circuit package comprises a first die with a conductive side, a plurality of lead posts where the conductive side of the first die faces the plurality of lead posts, and an encapsulating material encapsulating the first die and an end of the lead posts adjacent to the conductive side of the die.
Another aspect of the invention provides a method for packaging integrated circuits. Generally, a lead frame of a conductive material with a plurality of lead posts and a connecting sheet connecting the plurality of lead posts is provided. A plurality of first dice is attached to the lead frame, wherein each first die is electrically and mechanically connected to a plurality of the plurality of lead posts, and wherein a conductive side of each first die faces the plurality of lead posts. The plurality of dice is then encapsulated with an encapsulating material.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.


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U.S. patent application No. 09/054,422, entitled “Lead Frame Chip Scale Package”, filed Apr. 2, 1998, inventor(s): Shahram Mostafazadeh.
U.S. patent application No. 09/528,540, entitled “Leadless Packaging Process Using a Conductive Substrate”, filed Mar. 20, 2000, inventor(s): Bayan et al.
U.S. patent application No. 09/590,551, entitled “Lead Frame Design for Chip Scale Package”, filed Jun. 2, 2000, inventor(s): Shahram Mostafazadeh.
U.S. patent application No. 09/698,784, entitled “Flip Chip Scale Package”, filed Oct. 26, 2000, inventor(s): Shahram Mostafazadeh.

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