Chip scale packages and methods for manufacturing the chip...

Details Chip scale packages and methods for manufacturing the chip... Chip scale packages and methods for manufacturing the chip...

1998-12-28

2001-02-13

Potter, Roy (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S108000, C257S737000

Reexamination Certificate

active

06187615

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to chip scale packages and methods for manufacturing the packages at wafer level.
2. Description of Related Art
Miniaturization of electronic devices, which is one of major trends in the electronics industry, has led to the development of many technologies for manufacturing small packages, especially packages that have almost the same size as semiconductor integrated circuit chips. The Joint Electronic Device Engineering Council (JEDEC) has proposed the name ‘Chip Scale Package (CSP)’ for a type of small packages. JEDEC's definition of the CSP is a package having an outline that is 1.2 times or less than the outline of the semiconductor chip included in the package.
Many companies and institutes have developed their own CSP manufacturing technologies, and some have commercialized their own technologies or products. However, most of the newly developed CSPs have several drawbacks in the areas of product reliability, process reliability and manufacturing cost, when compared to plastic packages which are well established in the semiconductor industry. Therefore, for commercializing CSPs widely and successfully, new CSPs that have better process and product reliability and lower manufacturing costs are sought.
SUMMARY
In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a conductor layer for redistribution of the chip pads on a semiconductor chip, one or two insulation layers and solder bumps which function as the terminals of the CSP and are interconnected to respective chip pads by the conductor layer. In one embodiment, the conductor layer is formed directly on the surface or passivation layer of the semiconductor wafer, and in another embodiment, after an insulation layer is formed on the surface of the semiconductor wafer, the conductor layer is formed on the insulation layer. In both embodiments, another insulation layer is formed on the conductor layer, and additional metal layers can be formed between the chip pads and the conductor layer, and between the solder bumps and the conductor layer for improving the interface integrity.
In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer, which is formed on the top insulation layer, absorbs the stresses applied to solder bumps when a CSP is mounted on a circuit board and used for an extended period, and extends the life of the solder bumps. The edge protection layer is formed on the semiconductor wafer along the scribe lines on the semiconductor wafer, and the chip protection layer is form on the back of the semiconductor wafer. The edge protection layer and the chip protection layer prevent external forces from damaging the CSP. After forming all elements of the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.
The CSP manufacturing method according to the present invention employs currently available technology and thus, does not require development of new technology or equipment. Further, the wafer-level CSP manufacturing of the invention is more productive than a chip-level CSP manufacturing which fabricates CSPs one chip at a time after sawing a semiconductor wafer into integrated circuit chips.


REFERENCES:
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patent: 5903044 (1999-05-01), Farnworth et al.
patent: 5904546 (1999-05-01), Wood et al.
Mis et. al. (MCNC) 1996 ISHM Proceedings.
B. Rogers/D. Scheck; Solder Bumping/Redistribution using Photo-BCB (Cyclotene 4024) Delco Electronics (Kokomo) and Flip Chip Technologies (Pheonix) Nov. 12, 1996 (4 Pages).
Sandia's mini BGA; ®1994 TechSearch International, Inc. pp. 9 & 10.
M. Topper, J. Simon and H. ReichlTechnical University of Berlin; Redistribution Technology For Chip Scale Package Using Photosensitive BCB—Future Fab International publication pp. 363-368.
Dietrich Tonnles, Michael Topper, Jügen Wolf, Gunter Engelmann and Herbert Reichl; Mask aligners in advanced packaging—published in Solid State Technology (Mar. 1998).

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