Chip scale package using large ductile solder balls

Details Chip scale package using large ductile solder balls Chip scale package using large ductile solder balls

1997-10-20

2002-08-27

Wille, Douglas A. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S780000

Reexamination Certificate

active

06441487

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to flip chip mounting of integrated circuits to circuit boards or other mounting substrates via solder bumps, and more particularly, to a chip scale package and related method for allowing integrated circuits to be directly connected to an underlying circuit board or other substrate.
2. Description of the Related Art
Flip chips are conventionally understood by those skilled in the art to designate unpackaged integrated circuit chips that have contact pads bearing solder bumps for attachment to a patterned substrate. Such flip chips are formed from integrated circuit die that are scribed from a semiconductor wafer. During processing, such semiconductor wafer has an upper active surface through which impurities are introduced, by chemical diffusion and/or implantation, to form individual transistors and other electronic components. Metallization layers are also patterned upon the upper, or active, surface of such semiconductor wafer to electrically interconnect the electrodes of the various devices formed in such semiconductor wafer. For flip chips, the upper active surface of scribed integrated circuit die are inverted, or flipped, in order to be solder connected to an underlying patterned substrate. Heating of the solder bumps to their “reflow” temperature melts the solder, and the “reflow” of the solder joins the flip chip electrically and mechanically with the underlying patterned support substrate. The use of solder bumps to interconnect such flip chips to underlying support substrates is disclosed, for example, within U.S. Pat. No. 5,261,593 to Casson, et al.; within U.S. Pat. No. 5,220,200 to Blanton; within U.S. Pat. No. 5,547,740 to Higdon, et al.; and within U.S. Pat. No. 5,564,617 to Degani, et al.
Unpackaged integrated circuits are essentially bare semiconductor die, and are subject to damage if mishandled during assembly. Accordingly, many manufacturers of electronic equipment are reluctant to directly attach unpackaged flip chips to circuit boards, and many of such manufacturers desire devices that are “packaged”. Consequently, many integrated circuit suppliers have elected to “package” integrated circuits in a so-called “chip scale packages” to overcome customer concerns about handling bare die. A “chip scale package” typically designates a package that is no more than 20 percent larger than the integrated circuit die itself. Such chip scale packages provide a minimal degree of mechanical protection to the integrated circuit die and allow it to be handled more easily; customers tend to derive a sense of security knowing that they are not handling bare die. Such chip scale packages typically join the active surface of the integrated circuit to a somewhat larger substrate; electrical contacts provided on the substrate are then used to interconnect the chip scale package to the circuit board.
Often, the supporting substrate of a flip chip assembly and the associated integrated circuit will have different coefficients of thermal expansion. Such thermal stresses can fracture the solder bumps used to join the flip chip integrated circuit to the supporting substrate, causing the circuitry to fail. It is known to those in the flip chip packaging field to utilize an underfill material around the solder bumps, and between the integrated circuit and the supporting substrate, to constrain thermal expansion differences between the chip and the substrate. While the use of such underfill material serves to improves the fatigue life of the solder joints, the application of this underfill is often perceived as an expensive process that is not consistent with standard surface mount technology manufacturing processes.
Standard flip chip solder joints are typically very small (i.e., 100 micron diameter with a joined height of 70-85 microns). To be compatible with standard surface mount technology processes, the typical solder joint is composed of a 63 Sn/Pb solder, i.e., the solder bump is composed of 63% tin and 37% lead. In one known technology, 63 Sn/Pb solder is deposited onto a substrate's solder contact pads, and high percentage Pb solder bumps are evaporated or plated onto the flip chip bond pads of the integrated circuit; however, the size of such solder bumps was typically less than 7 mils (0.007 inch). The small solder joint, and the fatigue characteristics of these flip chip solder joints, mandate the use of an underfill to minimize the strain on the solder bumps.
Many known chip scale package processes use solder bumps to join the bonding pads of integrated circuit to the supporting substrate. These bonding pads are typically located at the outer perimeter of the integrated circuit chip. Complex integrated circuits often require in excess of one-hundred separate bonding pads in order to make the necessary power, input, and output connections between the integrated circuit and the outside world. Consequently, such bonding pads are typically disposed close to each other and place physical limitations upon the size and height of solder bumps overlying such bonding pads. While U.S. Pat. No. 5,547,740 to Higdon, et al. discloses that some of the solder bump contact pads can be redistributed internally, away from the outer perimeter of the integrated circuit, the size of such solder bumps is unchanged.
Moreover, most of the known techniques for forming chip scale packaging of integrated circuits must be practiced at the individual die level; i.e., the semiconductor wafer from which the integrated circuits are taken must first be scribed and cut into individual die before such chip scale packaging processes can be performed. These die level packaging techniques do not obtain the cost benefits of the wafer scale processing techniques. Moreover, certain integrated circuit markets, such as memory chips, are largely driven by form factor (i.e., the physical size of the packaged integrated circuit) and the cost of packaging. Yet, many of the known chip scale package techniques involve significant added cost and increase the dimensions of the packaged integrated circuit.
One of the known wafer level processing technologies used to form chip scale packages is the Mitsubishi PMEB (Plastic Molded, Extended Bump) technique; the PMEB package from Mitsubishi utilizes a redistribution technology to move solder bump pads away from the bond pads of the integrated circuit, and also performs initial solder bumping at the wafer level; however, following these steps, the Mitsubishi PMEB technique dices the components from the semiconductor wafer, encapsulates them, and then places a eutectic “extended bump” onto the surface of the package. The resulting chip scale package construction is sensitive to moisture ingress and has a relatively high cost at low lead counts. In addition, the Mitsubishi PMEB package uses a 63 Sn/Pb extended solder bump (the plastic encapsulant precludes a higher solder reflow temperature) which limits the fatigue life of the extended solder bumps.
Another known wafer level technology used to form chip scale packages is the Sandia Mini Ball Grid Array technique redistributes the locations of the solder bump locations on the integrated circuit, but requires multiple metal layers because a plating process is used for solder deposition. The redistribution wiring is provided by a first layer of deposited metal that is patterned and passivated. A second layer of metal is then sputtered over the wafer to form the solder bump pads, and standard electroplating processes are used for forming standard-sized solder bumps.
Accordingly, it is an object of the present invention to provide an improved chip scale package, and a method of forming such an improved chip scale package, for flip chip integrated circuits which is consistent with standard surface mount technology manufacturing processes, and which avoids the need to add an underfill material between the integrated circuit and a supporting substrate in order to protect the solder bumps from fatigue induced by thermal coefficient dif

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