Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-03-06
2004-11-09
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C174S267000, C257S690000, C716S030000
Reexamination Certificate
active
06815621
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip scale package, and to a printed circuit board on which chip scale packages are to be mounted so as to become integrated. More particularly, the present invention relates to the design of the layout of external terminals of the chip scale package, and to the corresponding layout of terminals and signal line (wiring) patterns of a printed circuit board.
2. Description of the Related Art
To meet the recent demands for miniaturization and high-speed operation in chip-based technology, chip packages are becoming lighter, thinner, and smaller. Moreover, the features that pose the most limits on the operating speed of the chip are the electrical characteristics of the chip package. In particular, the electrical characteristics of pins for connecting a chip with an external device can greatly affect the operating speed of the chip package. Thus, various kinds of chip packages have been developed around the physical structure and arrangement of their pins.
A chip package that operates at a low speed has a lead frame, and a plurality of pins arranged in a single row at one side of the package. However, such an arrangement poses a limitation on the number of the pins that can be accommodated, the limitation becoming more severe the smaller the package. Moreover, such an arrangement of pins is not suitable for a chip package required to perform a high-speed operation because large amounts of inductance, parasitic capacitance, resistance and the like occur between a bonding pad and the lead frame of the chip package.
To overcome such limitations, a chip scale package (CSP) has been developed in which a plurality of pins (or balls) are arranged along a grid, i.e., two-dimensionally. Such a chip scale package has an advantage in that the electrical parasitic factor of the pins (balls) is less than that of a comparable package comprising a lead frame. Thus, chip scale packages can be made small and yet operate at a high speed.
FIG. 1A
is a sectional view of a conventional chip scale package
10
known as a ball grid array (BGA) package. The BGA package
10
includes a semiconductor chip
13
which is electrically connected to I/O pins (solder balls)
12
. The chip
13
is supported on a printed circuit board (PCB)
11
. The PCB
11
also serves to connect the chip
13
to the pins (balls)
12
. A detailed description of BGA packages can be found in U.S. Pat. No. 6,041,495, the contents of which are hereby incorporated by reference.
FIG. 1B
is a plan view of the pin (ball) layout of the conventional chip scale package
10
. Basically, a plurality of the balls
12
are arranged regularly along a grid. When the chip scale package
10
constitutes a memory device, the balls
12
include balls dedicated, respectively, to transmit address and command signals, and to input or output data, and respective balls to be connected to ground and to a power source. In the figure, d
1
represents the distance between two adjacent balls
12
along one direction X in the grid, and d
2
represents the distance between two adjacent balls
12
along the other direction Y in the grid perpendicular to the first direction X.
A plurality of such chip scale packages are mounted on one surface of a printed circuit board (e.g., a mother board). The pins (balls) are spaced from one another by regular intervals d
1
, d
2
, and the pin (ball) lands of the printed circuit board that receive the pins (balls) of the chip scale package are thus also spaced from one another by regular intervals. As discussed in more detail below, only one signal line can be arranged between two adjacent pin (ball) lands. Consequently, all of the required signal lines can not be accommodated on the front surface of a printed circuit board to which the chip scale packages are mounted. Therefore, an additional wiring layer is required for facilitating signal lines, which layer contributes to the high production cost of the board using the chip scale package technology.
FIG. 2
is a plan view of such a printed circuit board on which a plurality of the chip scale packages are mounted. As shown in
FIG. 2
, eight chip scale packages
10
-
1
to
10
-
8
are mounted on the printed circuit board
100
. A terminal circuit
14
is arranged to one side (to the left in the figure) of the first chip scale package
10
-
1
. The terminal circuit
14
includes a plurality of pairs of a terminal resistor Rt and a terminal voltage Vt, which are connected in series with each other. The terminal circuit
14
is used to match the impedance of all of the signal lines common to the chip scale packages
10
-
1
to
10
-
8
. Input/output terminals
16
-
1
and
16
-
2
allow signals to be input and output to and from the printed circuit board
100
.
However, as was mentioned above, it is very difficult to accommodate all of the signal lines on the front surface of the printed circuit board
100
on which the chip scale packages
10
are mounted. This is because the balls
12
are disposed so close to one another that barely one signal line can pass therebetween. Therefore, most of the signal lines are provided on the other (lower) layers of the printed circuit board
100
.
Hereinafter, a configuration of a conventional printed circuit board, having an eight-layered structure, will be described below with reference to
FIGS. 3
to
9
. These figures are plan views of each of the layers (except for the sixth layer) of the conventional printed circuit board, respectively.
As shown in
FIG. 3
, the first layer has eight chip scale package regions
10
-
1
to
10
-
8
on which the chip scale packages are to be mounted. Ball lands
18
are provided on each of the chip scale package regions
10
-
1
to
10
-
8
at locations corresponding to the balls
12
of the chip scale package
10
(see
FIG. 1B
) to be mounted thereon. A via hole
20
is provided adjacent each ball land
18
for facilitating an electrical connection between the ball lands
18
and signal lines on the lower layers of the printed circuit board. Although not shown, the input and output terminals
16
-
1
and
16
-
2
shown in
FIG. 2
are connected as well through via holes
20
to signal lines on the lower layers of the printed circuit board.
As shown in
FIG. 4
, the second layer serves as a ground layer. Via holes
20
in the second layer which are depicted as triangles (for illustration only) serve as ground via holes. In particular, the “triangular” via holes
20
are electrically connected with certain ones of the ball pads
18
on the first layer of the printed circuit board
100
. Ground balls of the chip scale package
10
mounted on these ball pads are thus grounded via the triangular via holes
20
.
As shown in
FIG. 5
, the third layer has a plurality of via holes
20
that are electrically connected to the corresponding via holes in the second layer
20
, respectively. That is, the via holes
20
shown in
FIGS. 3 and 4
are filled with a conductive material so that an electrical connection is provided between the respective layers of the printed circuit board.
Note, the via holes
20
located on one side of the chip scale package regions
10
-
1
to
10
-
8
(the upper portion as viewed in the figures) are first via holes dedicated to address and command signal lines, and the via holes
20
located on the other side of the chip scale package regions
10
-
1
to
10
-
8
are second via holes dedicated to data lines for inputting and outputting data. Reference numeral
22
-
1
designates the address and command signal lines connected with respective ones of the first via holes
20
. The address and command signal lines
22
-
1
also pass between adjacent rows of the first via holes
20
. The data lines
24
-
11
to
24
-
81
are connected to the second via holes
20
, respectively. Although not shown, the address and command signal lines
22
-
1
and the data lines
24
-
11
to
24
-
81
are connected with corresponding ones of input and output terminals (e.g., the terminals
16
-
1
and
16
-
2
show
Lee Sang Won
Park Myun Joo
So Byung Se
Cuneo Kamand
Norris Jeremy
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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