Chip-scale package conversion technique for dies

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Manufacturing optimizations

Reexamination Certificate

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C716S055000, C716S119000, C716S137000, C716S138000, C700S098000, C700S120000, C700S121000, C438S107000, C438S123000, C257SE33056

Reexamination Certificate

active

07979813

ABSTRACT:
A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

REFERENCES:
patent: 6781248 (2004-08-01), Hui et al.
patent: 6984544 (2006-01-01), Cloud et al.
patent: 2002/0006686 (2002-01-01), Cloud et al.
patent: 2002/0074652 (2002-06-01), Pierce
patent: 2009/0311829 (2009-12-01), Yang et al.
patent: 2007134394 (2007-05-01), None

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