Chip-scale package

Details Chip-scale package Chip-scale package

1999-01-04

2002-06-25

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S786000, C257S773000, C257S690000, C257S780000, C257S500000

Reexamination Certificate

active

06410989

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packages and, more particularly to surface mount power semiconductor packages in which substantially all wire bonds from the semiconductor die to peripheral pad areas are directed to only one side of the package.
2. Related Art
Surface mount power semiconductor packages are known. These packages typically include a power semiconductor die disposed substantially at the center of a package and include a plurality of pads located at the periphery of the package. These pads are usually located is around substantially all of the available peripheral area of the package or at least two sides of the package.
One or more wire bonds are disposed between metalized areas of the power semiconductor die to one or more of the peripheral pads. This provides input/output connections between electrodes of the package and the semiconductor
It is desirable to utilize power semiconductor device packages exhibiting low total resistance, low thermal resistivity and high semiconductor die-to-package area ratios. Unfortunately, the prior art power semiconductor packages discussed hereinabove have not met each of these objectives at least because the large number of input/output pads disposed about the periphery the semiconductor package lowers the die to package area ratio. Package resistance and thermal conductivity also suffer when the input/output pads are disposed about the periphery of the package. These problems are exacerbated when multiple semiconductor die arrangements are desired, irrespective of whether the multiple semiconductor dies are mounted within the same package or in separate packages.
Accordingly, there is a need in the art for a new semiconductor package which ameliorates the problems of the prior art discussed above.
SUMMARY OF THE INVENTION
In order to overcome the disadvantages of prior art power semiconductor packages, the semiconductor package of the present invention includes a substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.
According to anther aspect of the invention, a semiconductor package includes a substrate having upper and lower surfaces, the upper surface including and a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a first power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a second power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a plurality of conductive pads disposed only at the second side edge of the substrate; a first set of wire bonds extending from the source metalized surface of the first MOSFET die to one or more of the plurality of conductive pads, at least one of the wire bonds extending from the gate metalized surface of the first MOSFET die to one of the conductive pads; and a second set of wire bonds extending from the source metalized surface of the second MOSFET die to one or more of the plurality of conductive pads, at least one of the wire bonds extending from the gate metalized surface of the second MOSFET die to one of the conductive pads.
Other features and advantages of the present invention will become apparent from the description of the invention taken in conjunction with the accompanying drawing.


REFERENCES:
patent: 4947234 (1990-08-01), Einzinger et al.
patent: 5019893 (1991-05-01), Frank et al.
patent: 5663869 (1997-09-01), Vinciarelli et al.
patent: 5665996 (1997-09-01), Williams et al.
patent: 5783866 (1998-07-01), Lee et al.
patent: 5930666 (1999-07-01), Pankove
patent: 6091089 (2000-07-01), Hiraga
patent: 6133632 (2000-10-01), Davis et al.

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