Chip scale package

Details Chip scale package Chip scale package

2001-05-10

2002-06-18

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C438S108000, C438S114000, C438S118000, C438S123000, C438S127000, C438S613000, C257S780000, C257S638000, C257S704000, C257S738000, C257S788000

Reexamination Certificate

active

06407459

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly to a chip scale package and a method for manufacturing the chip scale package at the wafer level, using a redistribution substrate.
2. Description of the Related Arts
The electronics industry has been progressing with the miniaturization of electronic devices. This trend influences semiconductor packaging technology, which enables the connection between bare IC chips and other components. Typically, a semiconductor package has a footprint much larger than that of the chip. To adapt to the miniaturization trend, the size difference between the package and the chip has been reduced, producing a new package type called a Chip Scale Package (or a Chip Size Package) (CSP). Among the manufacturing technologies for the CSPs is Wafer Level Chip Scale Packaging, which assembles CSPs at the wafer level, rather than separately processing individual chips.
FIG. 1
schematically shows a semiconductor wafer
10
, which includes integrated circuit chips
20
and scribe lines
14
dividing the chips
20
. As shown in
FIG. 2
which is an enlarged view of part ‘A’ of
FIG. 1
, chip pads
22
are on each chip
20
, and a passivation layer
24
covers the upper surface of the IC chip
20
except where openings through which the passivation layer
24
expose the chip pads
22
.
Regarding to
FIGS. 3 and 4
, in conventional wafer level chip scale packaging, a dielectric layer
36
and solder bumps
38
are formed on the surface of the wafer
10
. The solder bumps
38
electrically connect to the chip pads
22
of FIG.
2
. Then, a sawing apparatus separates the wafer
10
along the scribe lines
14
, producing individual CSPs
30
.
FIG. 4
illustrates the cross-sectional structure of the CSP
30
. The solder bump
38
connects to the chip pad
22
through a metal layer
34
, and a first and a second dielectric layers
32
and
36
are respectively on and under the metal layer
34
. Integrated circuits (not shown) are under the chip pad
22
and the passivation layer
24
. In the fabrication of the CSPs
30
on the wafer
10
, the first dielectric layer
32
is formed and patterned on the wafer
10
such that openings in the first dielectric layer
32
expose the chip pads
22
. Then, the metal layer
34
is formed on the first dielectric layer by metal deposition and patterning, so that the metal layer
34
contacts the chip pads
22
. The second dielectric layer
36
is formed on the metal layer
34
such that openings in the second dielectric layer
36
expose a portion of the metal layer
34
. Finally, solder bumps
38
are formed on the exposed portion of the metal layer
34
. As described above, sawing separates individual CSPs
30
.
The CSPs manufactured by the above-described manufacturing method have several problems. First, coating and high-temperature curing of the dielectric layers may apply thermal stress to the integrated circuits below the dielectric layers, damaging the integrated circuits. The thinner the dielectric layers are, the smaller the thermal stress is. However, making the dielectric layer thin increases the capacitance of the CSP. Second, when the CSP is mounted on an external circuit board such that the solder bumps contact the circuit board, the connection integrity between the solder bumps and the circuit board is not reliable.
Third, since defective chips as well as good chips are packaged in wafer level, the manufacturing cost of individual CSPs increases.
SUMMARY OF THE INVENTION
In accordance with the present invention a semiconductor package is provided which includes a semiconductor integrated circuit having a plurality if chip pads formed thereon, a plurality of interconnection bumps overlying on the chip pads, and a patterned metal layer connecting the interconnection bumps. A first dielectric layer is provided under the patterned metal layer, with the first dielectric layer having a plurality of first holes through which the patterned metal layer connects to the interconnection bumps. A second dielectric layer is provided overlying the patterned metal layer, with the second dielectric layer having a plurality of second holes. A plurality of terminal pads is provided, the plurality of terminal pads connecting the patterned metal layer through the second holes.


REFERENCES:
patent: 5895229 (1999-04-01), Carney et al.
patent: 6071755 (2000-06-01), Baba et al.
patent: 6287893 (2001-09-01), Elenius et al.

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