Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2000-01-31
2001-07-24
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S693000, C257S729000, C257S778000, C257S789000, C257S790000, C257S795000
Reexamination Certificate
active
06265768
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Field of the Invention
This invention relates to a chip scale package, and more specifically to a package body for use in encapsulating a semiconductor chip disposed on a substrate.
2. Description of the Related Art
FIGS. 1-3
illustrates three prior art chip scale packages. Typically a chip scale package comprises a semiconductor chip
110
disposed on the upper surface of a substrate
130
through an elastomer
120
, and a package body
150
for providing environmental sealing and electrical insulation for the semiconductor chip
110
. The package body
150
generally comprises a single layer structure formed of epoxy based material.
Normally, the semiconductor chip is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm ° C.
−1
and the substrate is usually formed of polymer having a coefficient of thermal expansion of 20-30 ppm ° C.
−1
. Since there is a significant difference between the semiconductor chip
110
and the substrate
130
in CTE, the semiconductor chip
110
and the substrate
130
expand and contract in different amounts along with temperature fluctuations. This imposes both shear and bend stresses on the package body
150
. Moreover, due to the flexible nature of the substrate, the substrate tends to warp or bend during packaging process and temperature fluctuations. This greatly magnifies the problems associated with the destructive stresses imposed on the package body
150
. And when the warpaged chip scale package is subject to pressure cook test (PCT) or other reliability tests, problems of peeling, delaminatoin or die cracking easily occur.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a chip scale package comprising a semiconductor chip disposed on a substrate wherein the semiconductor chip is sealed and electrically insulated by a package body comprising a multi-region structure, thereby reducing the problems of delamination or die-cracking.
The chip scale package according to a preferred embodiment of the present invention mainly comprises a semiconductor chip disposed on an upper surface of a substrate and sealed by a package body. The semiconductor chip has a plurality of bonding pads centrally formed on the active surface thereof. The substrate has a slot corresponding to the bonding pads of the semiconductor chip. The substrate is provided with a structure for making external electrical connection. And the bonding pads of the semiconductor chip are electrically connected to the structure for making external electrical connection.
The package body has a first portion formed on the upper surface of the substrate around the chip and a second portion formed within the slot of the substrate. The package body comprises a resin base material divided into a first region and a second region. The second region of the first portion of the package body is disposed between the first region of the first portion of the package body and the substrate. And the first region of the second portion of the package body is disposed between the second region of the second portion of the package body and the substrate. The resin base material contains a plurality of filler particles wherein the percentage by weight of the filler particles in the first region of the package body is smaller than that of the second region of the package body. Since the CTE of the filler particles is smaller than that of the resin base material, the CTE of the second region is smaller than that of the first region thereby buffering stresses due to CTE mismatch between the substrate and the chip. Besides, the content of the filler particles in the second region is larger; hence, the moisture from surrounding diffusing into the package is significantly reduced thereby reducing the problems of delamination or die-cracking.
The chip scale package according to another preferred embodiment of the present invention mainly comprises a semiconductor chip disposed on a upper surface of a substrate and sealed by a package body. The semiconductor chip has a plurality of bonding pads formed on two lateral sides of the active surface thereof. The substrate has at least two slots corresponding to the bonding pads of the semiconductor chip. The substrate is provided with a structure for making external electrical connection. And the bonding pads of the semiconductor chip are electrically connected to the structure for making external electrical connection.
The package body is formed on the upper surface of the substrate around the chip and fills the slots of the substrate. The package body comprises a resin base material divided into a first region and a second region wherein the second region is disposed between the first region and the substrate. The resin base material contains a plurality of filler particles wherein the percentage by weight of the filler particles in the first region of the package body is smaller than that of the second region of the package body. Since the CTE of the filler particles is smaller than that of the resin base material, the CTE of the second region is smaller than that of the first region thereby buffering stresses due to CTE mismatch between the substrate and the chip. Besides, the content of the filler particles in the second region is larger; hence, the moisture from surrounding diffusing into the package is significantly reduced thereby reducing the problems of delamination or die-cracking.
REFERENCES:
patent: 5216278 (1993-06-01), Lin et al.
patent: 5640047 (1997-06-01), Nakashima
patent: 5866949 (1999-02-01), Schueller
patent: 6013946 (2000-01-01), Lee et al.
patent: 7321244 (1995-12-01), None
Su Ching-Huei
Tao Su
Advanced Semiconductor Engineering Inc.
Graybill David E.
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