Chip-scale package

Details Chip-scale package Chip-scale package

2006-01-10

2006-01-10

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S784000, C257S786000, C257S773000, C257S690000

Reexamination Certificate

active

06984890

ABSTRACT:
A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.

REFERENCES:
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patent: 5665996 (1997-09-01), Williams et al.
patent: 5783866 (1998-07-01), Lee et al.
patent: 5930666 (1999-07-01), Pankove
patent: 6046499 (2000-04-01), Yano et al.
patent: 6091089 (2000-07-01), Hiraga
patent: 6133632 (2000-10-01), Davis et al.
patent: 6301122 (2001-10-01), Ishikawa et al.
patent: 6384492 (2002-05-01), Iversen

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