Chip scale package

Details Chip scale package Chip scale package

1998-04-07

2000-07-11

Kincaid, Kristine

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

257693, 257712, 257713, H01L 2348

Patent

active

060875860

ABSTRACT:
A chip scale package for packaging an IC chip includes a package frame displaced from the side and bottom surfaces of the IC chip by a predetermined gap and a pair of leads symmetrically extending in opposite directions. Each lead has an inner lead portion coupled to a bonding point on the top surface of the IC chip, and an outer lead portion bent and contoured in such a way that to follow the shape of the outside surface of the package frame. The lead further includes a connecting segment extending between the inner lead portion and the outer lead portion. Under heat induced stress, an angle between the connecting segment and the wall of the package frame changes causing displacement of the IC chip from its original position, and the gap between the surfaces of the IC chip and the package frame absorbs deviations in position of the IC chip, to cushion the stress effect.

REFERENCES:
patent: 4864079 (1989-09-01), Barlow
patent: 5206794 (1993-04-01), Long
patent: 5403975 (1995-04-01), Pasqualoni et al.
patent: 5592022 (1997-01-01), Richards et al.
patent: 5640045 (1997-06-01), Krause, III
patent: 5760471 (1998-06-01), Fujisawa et al.
patent: 5920458 (1999-07-01), Azar

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