Chip packaging structure adapted to reduce electromagnetic...

Details Chip packaging structure adapted to reduce electromagnetic... Chip packaging structure adapted to reduce electromagnetic...

2006-10-10

2006-10-10

Tran, Long (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S666000, C257S691000, C257S782000, C257SE23054

Reexamination Certificate

active

07119420

ABSTRACT:
A chip packaging structure adapted to reduce EMI includes a chip having contacts provided on one side thereof, and a leadframe having a plurality of leads arranged in a predetermined manner and provided at a bottom side with a conducting protrusion each for electrically connecting to external elements. The leadframe is fixedly attached to one side of the chip having the contacts provided thereon, and the leads are electrically connected at inner ends to the contacts via lead wires. An adhesive layer is applied to one side of the leadframe having the protrusions to thereby adhere a conducting layer to the leadframe with the protrusions downward extended through multiple through holes on the conducting layer; and at least one of the contacts on the chip is electrically connected to the conducting layer for the latter to serve as a ground or a power plane.

REFERENCES:
patent: 6614102 (2003-09-01), Hoffman et al.
patent: 7042071 (2006-05-01), Minamio et al.

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