Chip package with molded underfill

Details Chip package with molded underfill Chip package with molded underfill

1999-12-13

2001-11-27

Gaffin, Jeffrey (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S760000, C257S667000, C257S737000, C257S738000, C257S778000, C257S787000, C257S789000, C174S260000, C174S266000, C438S108000, C438S126000, C438S127000, C029S841000, C228S180220, C264S272170

Reexamination Certificate

active

06324069

ABSTRACT:

FIELD OF INVENTION
The invention relates to chip packages and a method used for manufacturing chip packages and, more particularly, to an integrated circuit chip package mounting system and a method of electrically connecting and mounting integrated circuit chips to a substrate.
BACKGROUND OF THE INVENTION
Flip chip technology is well known in the art for electrically connecting an integrated circuit chip to an integrated circuit substrate or package. Formation of one type of flip chip involves forming solder bumps on electrical interconnection pads on the active or front side of a semiconductor chip. The chip with solder bumps is prepared with a flux material and then is inverted onto a laminate substrate with the solder bumps aligned with metal circuits provided on the substrate. The flux cleans and activates the solder bumps for melting or reflowing. The solder bumps on the chip are then soldered to the metal pads on the substrate by melting the solder in a reflow furnace. A solder joint is formed by the reflowing of the solder between the semiconductor chip and the substrate. After the chip has been attached to the substrate by the reflow soldering process, narrow gaps are present between the solder bumps and between the chip and substrate. The gap between the chip and the substrate is determined by the height of the solder bumps, the flux preparation process, and the reflow process. Solder bumps have a tendency to reflow too much, resulting in a very narrow gap between the chip and the substrate. The current reflow process includes the use of a solder resist mask that covers the substrate surface to be mated with the solder bumps. An etching process removes the areas of the solder resist mask where the solder bumps are to reflow onto the circuit traces. If the gap between the chip and the substrate is too narrow, then the underfill process can be negatively affected since the capillary action is dependent on the size of the gap. Moreover, the underfill material may adhere to the solder resist mask which would further impede the capillary action of the underfill material during the underfilling process.
The substrate is typically comprised of a ceramic material or a polymer composite laminate while the chip is formed of silicon. For example, when the substrate is comprised of a polymer composite laminate and the semiconductor chip is formed of silicon, there is a mismatch in the coefficient of thermal expansion between the semiconductor chip and the substrate on which the chip is mounted. Dufng temperature cycling, the semiconductor chip and substrate expand and contract at differing rates. Accordingly, the soldered joints between the semiconductor chip and the substrate will have a tendency to fail because of the coefficient of thermal expansion mismatch. In addition, because of the very small size of the solder joints, the joints are subject to failures.
The strength of the solder joints between the integrated circuit chip and the substrate are typically enhanced by underfilling the space between the semiconductor chip and the substrate and around the solder joints. The underfill material is typically a polymer adhesive which reduces stress on the solder joints. A filler material may be added with the underfill material to improve the mechanical and electrical properties of the underfill material.
The conventional method of underfilling includes dispensing the underfill material in a fillet or bead extending along two or more edges of the chip and allowing the underfill material to flow by capillary action under the chip to fill all the gaps between the semiconductor chip and the substrate. The solder bumps create a very narrow gap between the semiconductor chip and the substrate which is about 0.002-0.005 inches (0.051-0.127 mm). Therefore, the underfill material which is capable of flowing through these narrow gaps contains only a small amount of filler material because the filler material will prevent the underfill material from flowing easily into the gaps. This type of underfill material with a low amount of filler material has an extremely high mismatch of coefficient of thermal expansion with the semiconductor chip, the solder bumps, and the substrate. Accordingly, it would be desirable to use an underfill material having more filler and thus, less of a thermal expansion coefficient mismatch with the substrate and chip. It would also be desirable to have means to control the height of the gap between the chip and the substrate during and after the reflow of the solder bumps.
An additional benefit of using an underfill material having more filler is that the filler material reduces moisture absorption. Where the underfill material absorbs less moisture, delamination between the underfill material and the substrate surface and/or the semiconductor chip is less likely to occur. Further, liquid adhering to the underfill material may result in contamination problems.
FIGS. 1 and 1
a
illustrate an example of an integrated circuit chip
100
which has been attached to a substrate
102
by solder bumps
104
and underfilled by a conventional method. The underfill material
114
has been drawn into the spaces between the solder bumps
104
by capillary action to fill the air spaces between the integrated circuit chip
100
and the substrate
102
.
FIG. 2
illustrates the substrate
102
with circuit traces
106
after the application of a liquid photo-irritable solder mask
108
, which is known in the art.
FIG. 3
illustrates the chip package before the soldering reflow process with the chip
100
spaced from the substrate
102
. The solder mask
108
has a series of openings
110
etched into the mask
108
to accept the solder bumps
104
during the reflow process.
FIG. 4
illustrates the chip package after the reflow process and after the underfilling process. The solder bumps
104
reflow to make electrical contact with the circuit traces
106
, and the resulting gap
112
is a function of the how much the solder bumps
104
melt and collapse during the reflow process. Then the gap is underfilled with underfill material
114
. If the gap
112
becomes too narrow during the reflow process, it is difficult to completely underfill the area between the chip
100
and the substrate
102
.
The use of capillary action to draw the underfill material into the gap between the integrated circuit chip and the substrate takes between 2 and 10 minutes, depending on many factors including the size of the chip, the size of the gap between the chip and the substrate, and the underfill material used. Another drawback of the conventional underfilling method is the occurrence of voids in the underfilling material, especially if the gap has become narrowed during the reflow process. Additionally, the conventional underfilling method does not allow for means to control the height of the gap between the chip and the substrate. Yet another drawback of the conventional underfilling method is that the underfill material does not bond well to the solder mask material.
Accordingly, a need exists for an underfilling method for completely filling the spaces between an integrated circuit chip and a substrate which can reliably underfill at a faster rate than known methods and wherein the height of the gap between the chip and the substrate after the reflow process is controlled. There also exists a need for an underfilling method that reduces or eliminates the use of the solder mask so that the underfill can bond directly to the substrate.
SUMMARY OF THE INVENTION
An integrated circuit chip package according to one aspect of the present invention includes an integrated circuit chip having an active surface with interconnection pads disposed thereon, and a substrate having a first surface with bonding pads substantially corresponding to the interconnection pads of the integrated circuit chip and a second side having a plurality of solder pads electrically interconnected with the bonding pads. A vent hole extends from the first side to the second side of the substrate and is positioned beneath th

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