Chip package with die and substrate

Details Chip package with die and substrate Chip package with die and substrate

2011-07-12

2011-07-12

Chambliss, Alonzo (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S700000, C257S723000, C257S758000, C257SE23019, C361S820000

Reexamination Certificate

active

07977763

ABSTRACT:
A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

REFERENCES:
patent: 5055321 (1991-10-01), Enomoto et al.
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 5388328 (1995-02-01), Yokono et al.
patent: 5432675 (1995-07-01), Sorimachi et al.
patent: 5483421 (1996-01-01), Gedney et al.
patent: 5548091 (1996-08-01), DiStefano et al.
patent: 5565706 (1996-10-01), Miura et al.
patent: 5663106 (1997-09-01), Karavakis et al.
patent: 5776796 (1998-07-01), DiStefano et al.
patent: 5834339 (1998-11-01), DiStefano et al.
patent: 5841193 (1998-11-01), Eichelberger
patent: 5874770 (1999-02-01), Saia et al.
patent: 5875545 (1999-03-01), DiStefano et al.
patent: 6008070 (1999-12-01), Farnworth
patent: 6030856 (2000-02-01), DiStefano et al.
patent: 6045655 (2000-04-01), DiStefano et al.
patent: 6046076 (2000-04-01), Mitchell et al.
patent: 6080605 (2000-06-01), DiStefano et al.
patent: 6093584 (2000-07-01), Fjelstad
patent: 6107123 (2000-08-01), DiStefano et al.
patent: 6121688 (2000-09-01), Akagawa
patent: 6126428 (2000-10-01), Mitchell et al.
patent: 6130116 (2000-10-01), Smith et al.
patent: 6168965 (2001-01-01), Malinovich
patent: 6169319 (2001-01-01), Malinovich
patent: 6177293 (2001-01-01), Netzer
patent: 6202299 (2001-03-01), DiStefano et al.
patent: 6204091 (2001-03-01), Smith et al.
patent: 6218215 (2001-04-01), DiStefano et al.
patent: 6221687 (2001-04-01), Abramovich
patent: 6225013 (2001-05-01), Cohen
patent: 6228687 (2001-05-01), Akram et al.
patent: 6232152 (2001-05-01), DiStefano et al.
patent: 6255738 (2001-07-01), DiStefano et al.
patent: 6284573 (2001-09-01), Farnworth
patent: 6285065 (2001-09-01), Levy
patent: 6288434 (2001-09-01), Levy
patent: 6294040 (2001-09-01), Raab et al.
patent: 6309915 (2001-10-01), DiStefano
patent: 6326697 (2001-12-01), Farnworth
patent: 6329224 (2001-12-01), Nguyen et al.
patent: 6359335 (2002-03-01), DiStefano et al.
patent: 6362498 (2002-03-01), Abramovich
patent: 6373141 (2002-04-01), DiStefano et al.
patent: 6383916 (2002-05-01), Lin
patent: 6388340 (2002-05-01), DiStefano
patent: 6396148 (2002-05-01), Eichelberger et al.
patent: 6429036 (2002-08-01), Nixon
patent: 6440834 (2002-08-01), Daubenspeck et al.
patent: 6445064 (2002-09-01), Ishii
patent: 6458681 (2002-10-01), DiStefano et al.
patent: 6460245 (2002-10-01), DiStefano
patent: 6555908 (2003-04-01), Eichelberger et al.
patent: 6602740 (2003-08-01), Mitchell
patent: 6610621 (2003-08-01), Masuko
patent: 6617174 (2003-09-01), Rotstein
patent: 6653172 (2003-11-01), DiStefano et al.
patent: 6673698 (2004-01-01), Lin et al.
patent: 6686015 (2004-02-01), Raab et al.
patent: 6746898 (2004-06-01), Lin et al.
patent: 6780747 (2004-08-01), DiStefano et al.
patent: 6800941 (2004-10-01), Lee et al.
patent: 6885107 (2005-04-01), Kinsman
patent: 7172922 (2007-02-01), Benjamin
patent: 7272888 (2007-09-01), DiStefano
patent: 7454834 (2008-11-01), DiStefano
patent: 2001/0021541 (2001-09-01), Akram et al.
patent: 2002/0006718 (2002-01-01), DiStefano
patent: 2002/0007904 (2002-01-01), Raab et al.
patent: 2002/0070443 (2002-06-01), Mu et al.
patent: 2002/0074641 (2002-06-01), Towle et al.
patent: 2002/0094671 (2002-07-01), DiStefano et al.
patent: 2002/0137263 (2002-09-01), Towle et al.
patent: 2002/0168797 (2002-11-01), DiStefano et al.
patent: 2002/0184758 (2002-12-01), DiStefano
patent: 2003/0027373 (2003-02-01), DiStefano et al.
patent: 2003/0122243 (2003-07-01), Lee et al.
patent: 2003/0122246 (2003-07-01), Lin et al.
patent: 2003/0205804 (2003-11-01), Lee et al.
patent: 2004/0046254 (2004-03-01), Lin et al.
patent: 2004/0084741 (2004-05-01), Boon
patent: 2004/0119097 (2004-06-01), Lee et al.
patent: 2004/0140556 (2004-07-01), Lin et al.
patent: 2004/0169264 (2004-09-01), Lee et al.
patent: 2005/0121771 (2005-06-01), Lin et al.
patent: 2005/0184358 (2005-08-01), Lin
patent: 2005/0208757 (2005-09-01), Lin
patent: 2006/0225272 (2006-10-01), DiStefano
patent: 403980 (2000-09-01), None
patent: 444370 (2001-07-01), None
patent: 531854 (2003-05-01), None
patent: 90123655 (2003-05-01), None
Microelectronic Packaging Handbook; Chapter 9, R.R. Tummala et al., Van Nostrand Reinhold, NY, 1989, pp. 673-725.
Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric.
Constant Materials, R.M. Emery et al., Itel Corp., Chandler, AZ.
Micro Electronic, Digital and Analog Circuits and Systems: p. 115 & p. 167, Jacob Millman.
Microelectronics Packaging Handbook (Second Edition), Technology Drivers Part I: An overview & 8-2 chip-level interconnection evolution, Rao R. Tummala, Eugene J. Rymaszewski & Alan G. Klopfenstein.
Chip Scale Package, Chapter ten 10.2, Design Concepts, and Package Structure: p. 157-p. 161, John H. Lau & S.W. Ricky Lee, McGraw Hill International, Electrical Series.
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006) pp. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369- 373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeoh, T-S. “ESD Effects on Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 773-776.
Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS Technology with Copper Metallization,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Jenei, S. et al. “High Q Inductor Add-on Module in Thick Cu/SiLK™ single damascene,” Proceedings from the IEEE International Interconnect Technology Conference (2001) pp. 107-109.
Groves, R. et al. “High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-on Module,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 149-152.
Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session 5, Microprocessors, 5.6 (2007) pp. 106-107, p. 590.
Kumar, R. et al. “A Family of 45nm IA Processors,” IEEE International Solid-State Circuits Conference, Session 3, Microprocessor Technologies, 3.2 (2009) pp. 58-59.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) Presentation Slides 1-6

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