Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2011-08-02
2011-08-02
Potter, Roy K (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S099000, C257SE23080
Reexamination Certificate
active
07989948
ABSTRACT:
A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.
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“First Office Action of China Counterpart Application”, issued on Feb. 24, 2011, p. 1-p. 8, in which the listed references were cited.
Chang Pin
Chen Chung-De
Hsieh Jui-Ching
Pan Li-Chi
Wang Chin-Horng
Industrial Technology Research Institute
Jianq Chyun IP Office
Potter Roy K
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