Chip package structure and fabricating method thereof

Details Chip package structure and fabricating method thereof Chip package structure and fabricating method thereof

2009-12-03

2011-10-18

Lee, Eugene (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S668000, C257S676000, C257S692000, C257SE23031, C257SE23032, C257SE23039, C257SE23153, C361S813000, C438S123000

Reexamination Certificate

active

08039946

ABSTRACT:
A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at least one bus bar, an insulating layer and transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar and the transfer bonding pads are disposed thereon. The inner leads and the bus bar are located above the active surface. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

REFERENCES:
patent: 5168368 (1992-12-01), Gow et al.
patent: 5293066 (1994-03-01), Tsumura
patent: 5723899 (1998-03-01), Shin
patent: 5917235 (1999-06-01), Imura
patent: 6686651 (2004-02-01), Foster
patent: 2002/0024122 (2002-02-01), Jung et al.
patent: 2003/0042583 (2003-03-01), Chen et al.

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