Chip package structure

Details Chip package structure Chip package structure

2008-05-20

2008-05-20

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

C257S787000, C257S790000, C257S778000, C257S777000, C257SE23127

Reexamination Certificate

active

10906536

ABSTRACT:
A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

REFERENCES:
patent: 5959363 (1999-09-01), Yamada et al.
patent: 6150193 (2000-11-01), Glenn
patent: 6265782 (2001-07-01), Yamamoto et al.
patent: 6308938 (2001-10-01), Futakuchi
patent: 6448665 (2002-09-01), Nakazawa et al.
patent: 6853089 (2005-02-01), Ujiie et al.
patent: 7009288 (2006-03-01), Bauer et al.

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