Chip package structure

Details Chip package structure Chip package structure

2007-12-18

2007-12-18

Zarneke, David A. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257SE23083

Reexamination Certificate

active

10974728

ABSTRACT:
This invention relates to a chip package structure comprising of a chip, multiple leads with inner and outer ends, an exposed chip upper surface, an encapsulated body encloses the peripherals of the chip, and multiple conducting wires used to connect electrically the chip and leads, wherein said leads extends internally to the surfaces on the two sides of the chip, in the mean time, pasting method is used to connect the two side surfaces of the chip to the leads in order to carry the chip, therefore, traditional die pad is replaced, furthermore, the outer ends or lower surfaces of the leads are exposed out of encapsulated body, this is to prevent solder overflow and enhance solder aggregation effect, in the mean time, packaging cost can be saved and easier visual positioning and rework can be obtained from this package structure, leads are used as terminals to be electrically connected to the external; therefore, through the internally extended leads structure, die pad is replaced, and the effects of package volume reduction, heat dissipation enhancement, packaging material cost saving and good, stable electrical connection are reached through this package structure.

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