Chip package structure

Details Chip package structure Chip package structure

2003-01-22

2004-03-16

Vigushin, John B. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S737000, C174S258000, C174S260000

Reexamination Certificate

active

06707162

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91217162, filed on Oct. 25, 2002.
BACKGROUND OF INVENTION
1 Field of Invention
The present invention relates to a chip package structure. More particularly, the present invention relates to a flip chip package structure having bonding columns instead of bumps as connective medium between an internal chip and an internal substrate.
2 Description of Related Art
Flip chip bonding technology is one of the principle techniques for forming a chip package. To form a flip chip package, bumps are formed on chip pads arranged as an array on the active surface of a chip. Next, the chip is flipped over so that the bumps are electrically and physically connected to corresponding bonding pads on a carrier (for example, a substrate or a printed circuit board (PCB)). Note that flip chip technique is able to produce a package having a higher pin count and occupying a smaller area. Moreover, average length of signal transmission paths is reduced considerably.
FIGS. 1A and 1B
are schematic cross-sectional views showing the structure before and after the assembling of a chip and a substrate to form a first type of conventional flip-chip package. First, as shown in
FIG. 1A
, the chip package structure
100
mainly includes a chip
110
and a substrate
120
. The chip
110
has an active surface
112
, a plurality of chip pads
116
, a passivation layer
114
and a plurality of bumps
118
. The active surface
112
of the chip
110
refers to the side of the chip
110
where most of the active devices are formed. The chip pads
116
are positioned on the active surface
112
of the chip
110
. The passivation layer
114
covers the active surface
112
of the chip
110
but exposes the chip pads
116
. The bumps
118
having a hemispherical profile are formed over the chip pads
116
. An under-bump-metallurgy (UBM) layer may also be formed between the chip pads
116
and the bump
118
to increase the bonding strength between the chip pads
116
and the bump
118
. In addition, the substrate
120
further includes a substrate surface
122
, a patterned circuit layer
124
and a solder mask layer
126
. The circuit layer
124
is located on the substrate surface
122
of the substrate
120
. The circuit layer
124
is a system comprising of a plurality of junction pads
124
a
and a plurality of trace lines
124
b
. The solder mask layer
126
is also located on the substrate surface
122
of the substrate
120
covering the circuit layer
124
. The solder mask layer
126
has a plurality of openings
126
a
that exposes the junction pads
124
a
. Hence, the flip chip
110
is able to attach to the substrate through the bumps
118
. An underfill material is also injected into the space between the chip
110
and the substrate
120
to form an underfill layer
130
. The underfill layer
130
protects the chip pads
116
, the bumps
118
and the junction pads
124
a.
Note that the junction pads
124
a
in
FIG. 1A
are solder mask defined (SMD) junction pads. Hence, the exposed area of the junction pads
124
a
is defined by the opening
126
a
in the solder mask layer
126
. Furthermore, the circuit layer
124
is normally fabricated using copper. To prevent surface oxidation of the junction pad
124
a
and increase bonding strength between the bump
118
and the junction pad
124
a
, stencil printing is often used to form a pre-solder block
128
inside the opening
126
a.
FIGS. 2A and 2B
are schematic cross-sectional views showing the structure before and after the assembling of a chip and a substrate to form a second type of conventional flip-chip package. As shown in
FIG. 2A
, the chip package
102
is similar to the chip package structure
100
in FIG.
1
A. The only difference between the two is in the junction pad portion of the substrate. In
FIG. 2A
, the junction pad
124
a
is a non-solder mask defined (NSMD) junction pad. The exposed area of the junction pad
124
a
is not defined by the opening
126
a
in the solder mask layer
126
. Because the circuit layer
124
is generally made using copper, a plating process is carried out to form a metallic layer
129
over the junction pad
124
a
to prevent surface oxidation of the junction pad
124
a
and increase the bonding strength between the bump
118
and the junction pad
124
a
. The metallic layer
129
can be a composite metallic layer such as a nickel/gold composite layer.
In general, an underfill dispense process is also required in the fabrication a conventional flip chip package. Here, capillary effect is utilized to carry underfill material into the space between the chip and the substrate before the underfill material solidifies into an underfill layer. The underfill material not only isolates various bumps electrically, but also buffers the bumps against lateral breakage due to thermal stress between the chip and the substrate produced by countless heating/cooling cycles. Note that voids are easily formed when the underfill material flows into the space between the chip and the substrate. Because voids are often the center of stress concentration and the residual gases inside these voids may expand when heated, reliability of the chip package is frequently reduced. Moreover, when the density of bumps between the chip and the substrate is high or the separation between the chip and the substrate is too small, underfill material may have difficulty getting into the space leading to considerable increase in void size and void density.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a chip package structure suitable for forming a flip chip package that eliminates the need for conducting an underfill dispensing process and hence lowering the probability of producing voids in the space between an internalized chip and an internalized substrate. Furthermore, even if the density of bumps on the chip is high, underfill material is still able to fill up all the gaps between the bumps, the chip and the substrate.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a chip package structure. The chip package structure at least includes a chip, a substrate and an underfill layer. First, a chip having an active surface with a plurality of chip pads and a plurality of bonding columns thereon is provided. The chip pads are positioned on the active surface of the chip. Each bonding column is connected to a corresponding chip pad. The substrate has a substrate surface, a solder mask layer, a plurality of junction pads and a plurality of trace lines. The substrate surface includes a chip junction region and a non-chip junction region. The junction pad and a portion of the trace lines are positioned within the chip junction region of the substrate surface. The remaining trace lines are positioned within the non-chip junction region of the substrate surface. Each bonding column is connected to a corresponding junction pad. In addition, the chip package structure further includes an underfill layer filling up the space bounded by the chip, the bonding columns and the substrate.
According to the chip package structure of this invention, the substrate may further include a patterned circuit layer on the substrate surface that forms the aforementioned junction pads and trace lines.
According to the chip package structure of this invention, the bonding column may further include a metallic layer positioned between each bonding column and its corresponding junction pad. The metallic layer can be a single metallic layer or a composite metallic layer having a plurality of metallic layers and the metallic layer can be fabricated using a single metallic element, an alloy or a combination of the two.
According to the chip package structure of this invention, the chip may further include a passivation layer covering the active surface of the chip but without completely covering the chip pads. The under

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