Chip package structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond

Reexamination Certificate

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Details

C257S790000, C257SE23021, C257SE23126, C257SE23127, C257SE23134, C257SE21503

Reexamination Certificate

active

07633169

ABSTRACT:
A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps is formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.

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patent: 5611481 (1997-03-01), Akamatsu et al.
patent: 5641113 (1997-06-01), Somaki et al.
patent: 6204089 (2001-03-01), Wang
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patent: 6255599 (2001-07-01), Chang et al.
patent: 6297553 (2001-10-01), Horiuchi et al.
patent: 6297560 (2001-10-01), Capote et al.
patent: 2001/0049187 (2001-12-01), Enomoto et al.

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