Chip package structure

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257SE25003, C257SE23151

Reexamination Certificate

active

07485953

ABSTRACT:
A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the substrate and has a plurality of first bonding pads arranged to reside on a first wire-bonding region of the first chip adjacent to the first contacts and are electrically connected to the first contacts via a plurality of first wires. The second chip is disposed on the first chip away from the symmetrical center of the first chip. The second chip has a plurality of second bonding pads arranged to reside on a second wire-bonding region of the second chip adjacent to the second contacts and are electrically connected to the second contacts via a plurality of second wires.

REFERENCES:
patent: 5721452 (1998-02-01), Fogal et al.
patent: 6359340 (2002-03-01), Lin et al.
patent: 6365966 (2002-04-01), Chen et al.
patent: 6461897 (2002-10-01), Lin et al.
patent: 6590279 (2003-07-01), Huang et al.
patent: 6784019 (2004-08-01), Huang
patent: 6858938 (2005-02-01), Michii
patent: 7262506 (2007-08-01), Mess et al.
patent: 7352057 (2008-04-01), Grafe et al.
patent: 2002/0011654 (2002-01-01), Kimura
patent: 454313 (2001-09-01), None
patent: M254725 (2005-01-01), None

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