Chip package, chip packaging, chip carrier and process thereof

Details Chip package, chip packaging, chip carrier and process thereof Chip package, chip packaging, chip carrier and process thereof

2005-09-27

2010-11-30

Fahmy, Wael M (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C257S686000, C257S692000, C257S698000, C257S738000, C257SE23067

Reexamination Certificate

active

07842597

ABSTRACT:
A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.

REFERENCES:
patent: 6879492 (2005-04-01), Alcoe et al.
patent: 6962829 (2005-11-01), Glenn et al.
patent: 7132741 (2006-11-01), Lin et al.
patent: 7232754 (2007-06-01), Kirby et al.
patent: 2004/0115919 (2004-06-01), Takaoka
patent: 2004/0124518 (2004-07-01), Karnezos
patent: 2005/0121768 (2005-06-01), Edelstein et al.

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