Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-12-18
2004-08-10
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S690000, C257S692000, C257S698000, C257S701000, C257S787000
Reexamination Certificate
active
06774492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and more particularly to a chip package, which is miniaturized and more simply manufactured by forming a conductive layer on both surfaces of a chip and by attaching a substrate provided with conductive via holes to one of these surfaces, and a method of manufacturing the chip package.
2. Description of the Related Art
As well known to those skilled in the art, semiconductor elements such as diodes or transistors are packaged and these packaged elements are then mounted on a printed circuit board. Structurally, this package easily connects terminals of the semiconductor chip to corresponding signal patterns of the printed circuit board and serves to protect the semiconductor chip from external stresses, thereby improving reliability of the package.
In order to satisfy recent trends of miniaturization of semiconductor products, the semiconductor chip packages also have been miniaturized. Therefore, a chip scale package has been introduced.
FIG. 1
is a schematic cross-sectional view of a conventional chip scale package. The structure of the chip scale package
10
of
FIG. 1
employs a ceramic substrate
1
and is applied to a diode with two terminals.
With reference to
FIG. 1
, two via holes, i.e., a first via hole
2
a
and a second via hole
2
b
, are formed on the ceramic substrate
1
. The first and the second via holes
2
a
,
2
b
are filled with a conductive material so as to electrically connect the upper and the lower surfaces of the first and the second via holes
2
a
,
2
b
. Then, a first and a second upper conductive lands
3
a
,
3
b
are formed on the upper surfaces of the first and the second via holes
2
a
,
2
b
, respectively. A first and a second lower conductive lands
4
a
,
4
b
are formed on the lower surfaces of the first and the second via holes
2
a
,
2
b
, respectively. The second upper conductive land
3
b
is directly connected to a terminal formed on the lower surface of the diode
5
, i.e., a mounting surface of the diode
5
, on a printed circuit board, and the first upper conductive land
3
a
is connected to the other terminal formed on the upper surface of the diode
5
by a wire
7
. A molding part
9
using a conventional resin is formed on the upper surface of the ceramic substrate
1
including the diode
5
in order to protect the diode
5
from the external stresses. Thereby, the manufacture of the package
10
is completed.
FIG. 2
is a schematic perspective view of a conventional chip package array.
As shown in
FIG. 2
, the manufactured chip package
10
is mounted on the printed circuit board
20
by a reflow soldering. The diode package
10
is electrically and mechanically connected to the printed circuit board
20
by arranging the upper conductive lands
3
a
,
3
b
and the lower conductive lands
4
a
,
4
b
of the package
10
on the corresponding signal patterns of the printed circuit board
20
and by then connecting the upper conductive lands
3
a
,
3
b
and the lower conductive lands
4
a
,
4
b
to the signal patterns with a solder
15
.
As shown in
FIGS. 1 and 2
, since the diode usually has terminals on its two opposite surfaces, these terminals should be interconnected by wires. However, these wires require a rather large space on the upper surface of the chip, thereby increasing the overall height of the package. Further, since either two or three via holes, corresponding to the number of the terminals of the chip, are formed on the ceramic substrate, an area as large as the total diameters of the via holes is further required. Moreover, in order not to connect the conductive lands formed on the upper and the lower surfaces of the via holes to each other, the conductive lands are spaced from each other by a designated interval. Therefore, the size of the substrate imposes a limit in miniaturizing the package.
Accordingly, a packaging technique, which can minimize the size of the package and simplify its manufacturing process, has been demanded.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a stable chip package, which is miniaturized, more simply manufactured and improves its reliability by forming a conductive layer on one surface of a chip and by attaching a substrate with conductive via holes to the other surface of the chip.
It is another object of the present invention to provide a chip package assembly, which is mounted on a printed circuit board by a innovative method according to the structure of the chip package.
It is a yet another object of the present invention to provide a method of manufacturing the chip package.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a chip package comprising a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip.
Preferably, a resin molding part formed along the outer wall of the chip mounted on the substrate may be further comprised. Further, preferably, a conductive layer may be formed on the upper and the lower surface of the substrate, and the upper and the lower conductive layers may be interconnected by the conductive via hole. The substrate may be a printed circuit board.
Further, preferably, the conductive via hole of the substrate may be formed on at least one side of the substrate in an approximately semicircular shape or on at least one corner of the substrate in an approximately quartered circular shape.
Moreover, preferably, the chip package may be applied to a diode element with two terminals or to a transistor element with three terminals. In case of the transistor element, the second surface of the chip may comprise two second terminals and the substrate may comprise two conductive via holes.
In accordance with another aspect of the present invention, there is provided a chip package assembly comprising a chip package and a printed circuit board. The chip package comprises a chip having a first conductive layer with a first terminal and a second conductive layer provided with at least one second terminal, the second conductive layer being opposite to the first conductive layer, and a substrate attached to the second conductive layer of the chip and including at least one conductive via hole connected to the second terminal of the chip. The printed circuit board comprises a plurality of signal patterns formed on the upper surface of the printed circuit board and connected to the terminals of the chip package, and a plurality of conductors for connecting the first conductive layer and the conductive via hole to the signal patterns. Herein, the chip package is vertically mounted on the upper surface of the printed circuit board so that the outer surfaces of the first conductive layer and the substrate become side surfaces.
Preferably, the conductor may be made of solder.
In accordance with yet another aspect of the present invention, there is provided a method of manufacturing a plurality of chip packages. The method comprises the steps of preparing a wafer having a plurality of chips spaced by a designated interval, preparing a substrate having a plurality of via holes spaced by the same interval as the chips, attaching the wafer to the upper surface of the substrate so that terminals formed on the lower surfaces of the chips are connected to the conductive via holes of the substrate, and sawing the chip assembly into a plurality of unit chip packages.
Preferably, a conductive layer may be formed on the upper and the lower surface of the su
Ahn Moon Bong
Cho Kwang Cheol
Oh Bang Won
Lowe Hauptman & Gilman & Berner LLP
Munson Gene M.
Samsung Electro-Mechanics Co. Ltd.
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