Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-02-16
2001-06-19
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S762000, C257S766000, C257S781000, C438S613000
Reexamination Certificate
active
06249053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip package and a method for manufacturing the same. More particularly, to a chip package of the type that has an interconnection pattern and ball pads formed by etching a metal layer on one side or both sides of a resin substrate, which includes a package, such as a BGA package, or a flip chip package and is mainly used as a package for mounting a chip, such as a LSI chip, and a method for manufacturing the same.
2. Description of the Relevant Art
Recently, a BGA (Ball Grid Array), a flip chip package, and the like, which can be made to have more terminals, have attracted attention since a semiconductor apparatus is requested to have a higher density and a higher speed. The BGA is most suitable for packaging of ICs, such as a microprocessor and an ASIC, which are required to have more terminals, and has the following characteristics.
(a) Since balls are arranged in a plane, it is possible to have more terminals than packaging technologies using a lead frame, such as a QFP (Quad Flat Package), and it is also possible to have still more terminals than a PGA (Pin Grid Array).
(b) Since a BGA has a larger lead pitch than the QFP, the precision of a mounter or the like is not always required to be high, and so the packaging yield is improved.
(c) The cost is relatively low.
(d) The heat dissipation property is excellent, so that the impedance can be low.
Until recently, attention had been paid to a ceramic BGA among BGAs from the viewpoint of reliability, but the priority is moving to plastic array packages from the viewpoint of cost reduction. In the plastic array packages of this kind, there are PBGA (Plastic BGA), TBGA (Tape BGA), &mgr;-BGA, CSP (Chip Size Package, Chip Scale Package) and the like in a broader sense.
An example of the PBGA is shown in FIG.
1
. On the IC chip
11
mounting surface of a resin substrate
12
, an interconnection pattern
13
is formed, while on the other surface thereof, a large number of ball pads
14
are formed. These ball pads
14
and the interconnection pattern
13
are connected through holes
16
for interconnection. The bottom surface of the IC chip
11
is connected to the ball pads
14
through through holes
17
for heat dissipation. On the ball pads
14
, solder balls
15
are deposited. The interconnection pattern
13
is connected to pads formed on the IC chip
11
(not shown) through bonding pads
13
a
and wire bonders
18
. The portion which includes the IC chip
11
, the wire bonders
18
, and the majority of the interconnection pattern
13
is covered with a mold resin
19
.
Ordinarily, the bonding pads
13
a
and the ball pads
14
are Ni/Au plated (not shown) in order to improve the bonding property and the deposition property of the solder balls
15
, and for that purpose the interconnection for electroplating is formed as shown in
FIG. 2
, for example. Each of the bonding pads
13
a
and ball pads
14
is connected to a tie bar
21
through a lead for plating
20
. After the plating is finished, each device is made by cutting on cutting lines
22
. The portion which need not be plated is previously covered with a solder mask
23
before the plating treatment.
An example of a BGA with a heat spreader is shown in
FIGS. 3 and 4
. BT (Bismaleimide Triazine) is used for forming a tape-shaped thin resin substrate
32
. Since the BT resin has almost the same thermal transformation temperature (300° C.) as a polyimide resin and has better adhesiveness to a copper foil and workability than the polyimide resin, it is used widely for LSI packages. On the bottom surface of the resin substrate
32
, an interconnection pattern (not shown) and ball pads
34
are formed by etching a copper foil. On the ball pads
34
, solder balls
15
are deposited. Onto the top surface of the resin substrate
32
, a Cu ring
33
having a cavity
35
to accommodate an IC chip
11
is adhered. Onto the top surface of the Cu ring
33
, a Cu heat spreader
38
is further adhered through an adhesive sheet
38
a
. In the center portion of the resin substrate
32
, a dam
36
is formed so as to surround the cavity
35
. After connecting wire bonders
18
, an injection mold resin
39
is injected into the cavity
35
to be solidified. The ball pads
34
and bonding pads (not shown) comprise a Cu layer
34
a
and a Ni/Au layer
34
b
as shown in
FIG. 4. A
solder mask
43
is formed around the Ni/Au layer
34
b.
In the BGA with a heat spreader of the type shown in
FIG. 3
, since it is difficult to arrange the leads for plating
20
shown in
FIG. 2
from the viewpoint of space, the Ni/Au layer
34
b
is formed by electroless plating. The leads for plating
20
and tie bars
21
shown in
FIG. 2
are not formed during the manufacturing process.
An example of a conventional flip chip package wherein a semiconductor component is mounted by flip chip bonding is shown in
FIGS. 5 and 6
. On the chip
11
mounting surface of a resin substrate
12
, an interconnection pattern
13
and ball pads
14
a
are formed, while on the other surface thereof, a large number of ball pads
14
b
are formed. These ball pads
14
b
and the interconnection pattern
13
are connected through through holes
16
for interconnection. The ball pads
14
a
under the chip
11
are connected to the ball pads
14
b
through through holes
17
for heat dissipation. On the ball pads
14
b
. solder balls
15
are deposited. The interconnection pattern
13
is connected to the chip
11
through the solder balls
15
deposited on the ball pads
14
a
. The space between the chip
11
and the resin substrate
12
is charged with a mold resin
19
. On the portion of the interconnection pattern
13
except the ball pads
14
a
and
14
b
, a solder mask
23
is formed. The ball pads
14
a
and
14
b
comprise a Cu layer
34
a
and a Ni/Au layer
34
b
as shown in FIG.
6
and the solder mask
23
is formed around the Ni/Au layer
34
b.
The Ni/Au layer
34
b
in the flip chip package shown in
FIGS. 5 and 6
is formed not by electroplating but by electroless plating. This is because flip chip packages tend to have high-density interconnections, and so it is difficult to form leads for electroplating between the high-density interconnections.
In the PBGA of the type shown in
FIGS. 1 and 2
, a large number of leads for plating
20
connected to each bonding pad
13
a
or ball pad
14
and tie bars
21
must be formed for electroplating, which prevents the interconnection pattern
13
and ball pads
14
from having a higher density. The leads for plating
20
inside the cutting lines
22
are left even after plating, leading to a possibility that they become a source of reflected noise, which adversely affects the electrical properties.
On the other hand, since the electroless plating is conducted in the BGA with a heat spreader of the type shown in
FIGS. 3 and 4
, the leads for plating
20
and the tie bars
21
need not be formed, and so there is no problem with density increasing of the interconnections and the like. However, the adhesive strength of the solder balls
15
to the ball pads
34
is low, so that the adhesion tends to be unstable.
Since the electroless plating is conducted in the flip chip package of the type shown in
FIGS. 5 and 6
in the same manner as in the BGA with a heat spreader of the type shown in
FIGS. 3 and 4
, the leads for plating
20
and the tie bars
21
need not be formed and so there is no problem with increasing density of the interconnections and the like. However, the adhesive strength of the solder balls
15
to the ball pads
14
a
and
14
b
is low, so that the adhesion tends to be unstable.
SUMMARY OF THE INVENTION
The present invention was developed in order to solve the above problems. It is an object of the present invention to provide a chip package wherein leads for plating need not be formed so as to enable the realization of higher density and an improvement of electrical properties while the plating is conducted by electroplating so that the adhesive strength o
Kasai Takeshi
Nakata Yoshikazu
Lee Eddie C.
Sumitomo Metal (SMI) Electronics Devices Inc.
Wenderoth , Lind & Ponack, L.L.P.
Wilson Allan R.
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