Chip package and method

Details Chip package and method Chip package and method

1999-10-25

2002-05-21

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S737000, C257S738000, C257S778000, C257S700000, C257S701000, C257S758000, C174S266000, C174S255000, C361S760000, C361S794000, C428S209000, C029S843000, C029S840000

Reexamination Certificate

active

06392301

ABSTRACT:

FIELD
The present invention relates generally to computer board and chip packaging, and more specifically to chip package design and manufacturing.
BACKGROUND
As input/output (I/O) speed and the total number of I/Os required for high performance semiconductor chips have increased dramatically, the need for increased numbers of interconnect lines with low line impedance variation in chip packages has increased as well. To address this need, manufacturers have used multi-layered packages where several layers of conductors are separated by layers of dielectric material.
In printed circuit board (PCB) and integrated circuit (IC) manufacture, often semiconductor dice are to be connected to a motherboard. Typically, a die is connected to a package, which is in turn connected to a motherboard. The motherboard typically receives multiple packages, thereby providing electrical connections between multiple semiconductor chips. One manner in which circuit dice can be mounted to a package is to “flip mount” the die to a small board designed to receive the die. When flip mounted, the die couples electrical signals to the package without the use of bond wires.
The package can have a core made of a common material such as glass epoxy, and can have additional layers laminated onto the core. These additional layers are also known as “build-up” layers. The build-up layers are typically formed from alternating layers of dielectric material and conductive material. Patterns may be built in the metal or conductive layer through various etching processes such as wet etching which are known in the art and will not be described further herein. Plated through holes called vias are used to make interconnects between various layers of metal. Using these layers and vias, several layers of interconnections may be built up.
Input/Output functions are typically accomplished using metal traces within the layers. Each trace has an impedance generated by its geometry and location in the package. Due to the manufacturing technology and material requirements, packages having build-up layers often include a number of degassing holes in the metal layers. Degassing holes allow gas to be evaporated from dielectric material during the manufacture of the package so that bubbles do not form in the package.
Traces may be routed over or under the degassing holes, or around the degassing holes, or a combination thereof. Since the traces are not in the same location on the package, and pass over varying amounts of non-metal areas caused by degassing holes in the metal layers, the traces have an impedance variation, or mismatch. A typical degassing hole pattern has a grid-like array of degassing holes aligned vertically between two layers, as is shown in FIG.
1
. In
FIG. 1
, the degassing holes
102
of the top and bottom layers are exactly aligned in the x and y directions. When traces such as trace
1
and trace
2
are used with a degassing hole alignment scheme as shown in
FIG. 1
, trace
1
has less metal from the conductive layers both above and below the trace than trace
2
, and an impedance variation between the traces results.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a semiconductor package having reduced trace impedance variation.
SUMMARY
In one embodiment, a method of specifying the location of a plurality of apertures in a conductive layer includes defining a plurality of polygons on a first plane, where the first plane represents the conductive layer, and the polygons represent candidate locations for apertures in the conductive layer. The method further includes defining a plurality of signal traces on a second plane, where the second plane represents a routing layer to be parallel to the conductive layer, and then superimposing the second plane on the first plane such that at least one signal trace crosses over at least one of the polygons, creating at least one region of intersection. The method further includes removing the at least one region of intersection from the at least one of the plurality of polygons.
In another embodiment, a device package includes a first dielectric layer having a first side and an opposing side, and a plurality of metal traces disposed on the first side of the first dielectric layer, where the plurality of metal traces are routed generally radially outward from a first region on the package. The package further includes a first conductive layer disposed on the opposing side of the first dielectric layer, where the first conductive layer has apertures therethrough, the apertures being positioned generally in a radial pattern outward from the first region, and where the apertures lie between adjacent traces such that the adjacent traces do not overlap the apertures.


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