Chip package

Details Chip package Chip package

2011-06-21

2011-06-21

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S777000, C257SE23141, C257SE23021

Reexamination Certificate

active

07964961

ABSTRACT:
A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers.

REFERENCES:
patent: 5226232 (1993-07-01), Boyd
patent: 5261155 (1993-11-01), Angulas et al.
patent: 5534465 (1996-07-01), Frye et al.
patent: 5631499 (1997-05-01), Hosomi et al.
patent: 5883435 (1999-03-01), Geffken et al.
patent: 6013571 (2000-01-01), Morrell
patent: 6077726 (2000-06-01), Mistry et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6177731 (2001-01-01), Ishida et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6229711 (2001-05-01), Yoneda
patent: 6426281 (2002-07-01), Lin et al.
patent: 6479900 (2002-11-01), Shinogi et al.
patent: 6673698 (2004-01-01), Lin et al.
patent: 6683380 (2004-01-01), Efland et al.
patent: 6707159 (2004-03-01), Kumamoto et al.
patent: 6746898 (2004-06-01), Lin et al.
patent: 6756664 (2004-06-01), Yang
patent: 6762122 (2004-07-01), Mis et al.
patent: 6791178 (2004-09-01), Yamaguchi et al.
patent: 6800941 (2004-10-01), Lee et al.
patent: 6853076 (2005-02-01), Datta et al.
patent: 6940169 (2005-09-01), Jin et al.
patent: 7045899 (2006-05-01), Yamane et al.
patent: 7220657 (2007-05-01), Ihara et al.
patent: 7413929 (2008-08-01), Lee et al.
patent: 7511376 (2009-03-01), Lin et al.
patent: 7569422 (2009-08-01), Lin
patent: 2001/0040290 (2001-11-01), Sakurai et al.
patent: 2002/0037643 (2002-03-01), Ishimaru
patent: 2002/0043723 (2002-04-01), Shimizu et al.
patent: 2003/0006062 (2003-01-01), Stone et al.
patent: 2003/0218246 (2003-11-01), Abe et al.
patent: 2004/0007779 (2004-01-01), Arbuthnot et al.
patent: 2005/0093149 (2005-05-01), Nakatani
patent: 2008/0284037 (2008-11-01), Andry et al.
patent: 1536469 (2005-06-01), None
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006) pp. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369-373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeoh, T-S. “ESD Effects On Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 773-776.
Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS Technology with Copper Metallization,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Jenei, S. et al. “High Q Inductor Add-on Module in Thick Cu/SiLK™ single damascene,” Proceedings from the IEEE International Interconnect Technology Conference (2001) pp. 107-109.
Groves, R. et al. “High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-on Module,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 149-152.
Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session 5, Microprocessors, 5.6 (2007) pp. 106-107, p. 590.
Kumar, R. et al. “A Family of 45nm IA Processors,” IEEE International Solid-State Circuits Conference, Session 3, Microprocessor Technologies, 3.2 (2009) pp. 58-59.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) Presentation Slides 1-66.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) pp. 23-28.
Ingerly, D. et al. “Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing,” International Interconnect Technology Conference (2008) pp. 216-218.
Kurd, N. et al. “Next Generation Intel® Micro-architecture (Nehalem) Clocking Architecture,” Symposium on VLSI Circuits Digest of Technical Papers (2008) pp. 62-63.
Maloney, T. et al. “Novel Clamp Circuits for IC Power Supply Protection,”IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C, vol. 19, No. 3 (Jul. 1996) pp. 150-161.
Geffken, R. M. “An Overview of Polyimide Use in Integrated Circuits and Packaging,” Proceedings of the Third International Symposium on Ultra Large Scale Integration Science and Technology (1991) pp. 667-677.
Luther, B. et al. “Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices,” Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference (1993) pp. 15-21.
Master, R. et al. “Ceramic Mini-Ball Grid Array Package for High Speed Device,” Proceedings from the 45th Electronic Components and Technology Conference (1995) pp. 46-50.
Maloney, T. et al. “Stacked PMOS Clamps for High Voltage Power Supply Protection,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings (1999) pp. 70-77.
Lin, M.S. et al. “A New System-on-a-Chip (SOC) Technology—High Q Post Passivation Inductors,” Proceedings from the 53rd Electronic Components and Technology Conference (May 30, 2003) pp. 1503-1509.
MEGIC Corp. “MEGIC way to system solutions through bumping and redistribution,” (Brochure) (Feb. 6, 2004) pp. 1-3.
Lin, M.S. “Post Passivation Technology™—MEGIC® Way to System Solutions,” Presentation given at TSMC Technology Symposium, Japan (Oct. 1, 2003) pp. 1-32.
Lin, M.S. et al. “A New IC Interconnection Scheme and Design Architecture for High Performance ICs at Very Low Fabrication Cost—Post Passivation Interconnection,” Proceedings of the IEEE Custom Integrated Circuits Conference (Sep. 24, 2003) pp. 533-536.

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