Chip-on-chip interconnections of varied characterstics

Details Chip-on-chip interconnections of varied characterstics Chip-on-chip interconnections of varied characterstics

2000-10-18

2003-11-04

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S777000, C257S723000

Reexamination Certificate

active

06642080

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to chip-on-chip interconnections in semiconductor devices.
2. Background Art
In the past, semiconductor devices built with different technologies were fabricated on separate wafers, diced, and then connected together by mounting the devices on a substrate. Recently, the merging of DRAM and logic, and other dissimilar semiconductor technologies has been headed towards connecting one chip directly to another chip through solder ball connections, such as C4 (controlled collapse chip connection) connections. This structure, known as a face-to-face chip-on-chip (chip
1
/chip
2
) structure, provides a large number of I/O's between the two chips and is shown in the following IBM Technical Disclosure Bulletins: Vol. 28 No. 2, July 1985 “Mated Array Chip Configuration”,pgs. 811-812; and Vol. 25 No. 10, March 1983 “Chip-On-Chip Module for Assembly” by Spector et al., pgs. 5315-5316. Although the chip
1
/chip
2
structure of the aforementioned bulletins and other similar structures are joined through C4 technology, there is a limit to how the connections can be made between the chips as well as connections made to the outside package. Thus, other chip-on-chip connections, such as wirebonding, are necessary to connect the chip
1
/chip
2
structure to other chips or to the outside package. These other connections may not be as easily manufactured or as durable as the C4 solder ball connection.
SUMMARY OF THE INVENTION
It is thus an advantage of the present invention to provide chip-on-chip interconnections of varied characteristics that eliminate the above described limitations.
The advantages of the invention are realized by chip-on-chip interconnections (e.g., C4 interconnections, solder ball interconnections, polyimer-metal composite interconnections, plated copper columns, micro-velcro connections, etc.) of varied diameters, heights and/or composition, allowing for connections between devices and substrates at different levels or composition. That is, a first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for a first and second chip-on-chip connection to other packages, substrates or chips.


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