Chip-on-chip connection with second chip located in...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S777000, C257S686000, C257S723000, C257S779000, C257S737000, C257S738000, C257S680000, C257S431000, C257S432000, C257S433000, C257S668000, C257S774000, C361S761000, C361S764000, C361S748000, C361S803000

Reexamination Certificate

active

07045901

ABSTRACT:
A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

REFERENCES:
patent: 4598307 (1986-07-01), Wakabayashi et al.
patent: 5475262 (1995-12-01), Wang et al.
patent: 5498906 (1996-03-01), Roane et al.
patent: 5608262 (1997-03-01), Degani et al.
patent: 5789303 (1998-08-01), Leung et al.
patent: 5814871 (1998-09-01), Furukawa et al.
patent: 5818748 (1998-10-01), Bertin et al.
patent: 5854534 (1998-12-01), Beilin et al.
patent: 5869894 (1999-02-01), Degani et al.
patent: 5898223 (1999-04-01), Frye et al.
patent: 5926061 (1999-07-01), Usui
patent: 5939782 (1999-08-01), Malladi
patent: 5963110 (1999-10-01), Ihara et al.
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6140144 (2000-10-01), Najafi et al.
patent: 6144507 (2000-11-01), Hashimoto
patent: 6154370 (2000-11-01), Degani et al.
patent: 6297551 (2001-10-01), Dudderar et al.
patent: 6437430 (2002-08-01), Yamada
patent: 6512861 (2003-01-01), Chakravorty et al.
patent: 6521984 (2003-02-01), Matsuura
patent: 6566745 (2003-05-01), Beyne et al.
patent: 2002/0053723 (2002-05-01), Matsuura
patent: 2002/0079568 (2002-06-01), Degani et al.
patent: 2002/0096781 (2002-07-01), Toyosawa
patent: 2002/0175421 (2002-11-01), Kimura
patent: 2003/0183934 (2003-10-01), Barrett
patent: 2003/0209808 (2003-11-01), Baba
patent: 3-16159 (1991-01-01), None
Takahashi, et al., “3-Dimensional Memory Module”, Semi, pp. 166-167, (1997).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Chip-on-chip connection with second chip located in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip-on-chip connection with second chip located in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip-on-chip connection with second chip located in... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3646433

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.