Chip level scan chain planning for hierarchical design flows

Details Chip level scan chain planning for hierarchical design flows Chip level scan chain planning for hierarchical design flows

2006-12-12

2010-02-02

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S726000

Reexamination Certificate

active

07657850

ABSTRACT:
A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.

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