Chip layout for implementing arbitrated high speed switching...

Details Chip layout for implementing arbitrated high speed switching... Chip layout for implementing arbitrated high speed switching...

1998-10-29

2001-05-22

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C711S101000, C710S120000, C365S185110

Reexamination Certificate

active

06237130

ABSTRACT:

The present invention relates to microelectronic chips for enabling high speed I/O data port communication with network DRAM banks, and the like, being more particularly, though not exclusively, directed to chip layouts particularly tailored for operation with the universal multi-port internally cached DRAM bank high speed switching techniques described in Mukesh Chatter U.S. Pat. No. 5,799,209 and published in PCT publication document WO97/24725.
BACKGROUND
Many approaches have been used for the layout of various types of network switching and communication chips. Prior chip layout schemes have not, however, been suited to accommodating the operation and extremely high switching speeds and other quite different characteristics of the above-mentioned Chatter, universal multi-port internally cached DRAM bank operation. In such, wherein there is provided a switching module logic control for connecting any of the I/O resources through serial interfaces with any I/O resource buffer competing for access to a common bus under a dynamic configuration of switching allocation appropriate for the desired data routability among the interfaces—with the switching module assigning any buffer to any serial interface and without any intermediate step of data transfer—prior chip layout schemes have not been suited to accommodating this operation and the extremely high switching speeds attainable therewith. The common bus access competition may be with an external competing CPU or similar control data ports, if used, competing for common system bus access with the I/O data resources serially interfaced with the internally cached DRAMs, sometimes referred to as “macros”, and/or the competition of the I/O resource data buffers themselves for access to a common internal line bus within the DRAM bank, as described in said patent.
OBJECTS OF INVENTION
A primary object of the present invention, accordingly, is to provide a new and improved chip layout particularly designed for implementing said multi-port internally cached DRAM bank high speed switching techniques and the like, and in a highly efficient and economical manner.
Other and further objects will be explained hereinafter and are more particularly pointed out in connection with the appended claims.
SUMMARY
In summary, the invention embraces, a chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, in combination, a chip surface carrying a plurality of closely packed DRAM banks, data ports, SRAM buffer banks, arbitration units and busses therefor, and along the outer peripheral edges of which
110
connector pins are positioned; each of the DRAM banks being provided with its own transmit/receive SRAM buffer bank and positioned with respect thereto on the chip to allow the shortest length for communication with its buffer bank busses; half of the DRAM banks being distributed in spaced symmetrical rows in the upper half of the chip, and the other half of the DRAM banks being distributed in symmetrical rows in the lower half of the chip; the data ports being positioned along vertical-horizontal cross arms dividing the chip surface into symmetrical quadrants, each containing a quadrant of the DRAMs; the receive and transmit SRAM buffer banks of each DRAM being located in the space between the DRAMs in each quadrant such that the buffer banks of adjacent DRAMS are adjacent to one another; an arbitration unit positioned adjacent each receive SRAM buffer bank for each DRAM and contiguous with the arbitration unit of the next DRAM, with data ports substantially symmetrically placed, and with each data port connected to each arbitration unit and each transmit/receive buffer bank; each data port being enabled to write into any DRAM bank by connections effected such that each data port is substantially symmetric with respect to the DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed to minimize clock skew by symmetric clock distribution.
Preferred and best mode chip designs and configurations are later detailed.


REFERENCES:
patent: 5438681 (1995-08-01), Mensch, Jr.
patent: 5890195 (1999-03-01), Rao
patent: 5953738 (1999-09-01), Rao
patent: 6088760 (2000-07-01), Walker et al.
patent: 6088785 (2000-07-01), Hudson et al.
Heshami et al., “A 250-MHZ Skewed-Clock Pipelined Data Buffer”, IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1996, pp. 376-383.*
Heshami et al., “A 250-MHZ Skewed-Clock Pipelined Dual-Port Embedded DRAM”, IEEE 1995 Custom Integrated Circuits Conference, Jan. 1995, pp. 143-146.

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