Chip initialization signal generating circuit

Details Chip initialization signal generating circuit Chip initialization signal generating circuit

1994-07-06

1995-11-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327143, 327 77, 327 78, H03K 1722, H03K 5153, H03K 17687

Patent

active

054670390

ABSTRACT:
A circuit which is particularly useful as a chip initialization signal generating circuit for initializing the circuits of a semiconductor memory device includes a time delay circuit for generating a second signal a predetermined time after a first signal, e.g., a power supply voltage, is applied thereto, a first inverter for generating a third signal having a first logic level when the second signal is below a trip point level of the first inverter, and a second logic level when the second signal is above the trip point level, and, a trip point level raising circuit coupled to the first inverter for raising the trip point level. The circuit preferably further includes a second inverter for generating a fourth signal having a logic level which is the inverse of the third signal, a direct current path cutoff circuit coupled to the second inverter for cutting off a direct current path through the second inverter, and a buffer circuit for producing the chip initialization signal by appropriately shaping the fourth signal.

REFERENCES:
patent: 4558233 (1985-12-01), Nakamori
patent: 4633107 (1986-12-01), Norsworthy
patent: 4902910 (1990-02-01), Hsieh
patent: 4939385 (1990-07-01), Dubujet
patent: 5212412 (1993-05-01), Atriss et al.
patent: 5278458 (1994-01-01), Holland et al.
patent: 5287011 (1994-02-01), Koshikawa et al.

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