Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Patent
1997-10-06
2000-12-12
Kincaid, Kristine
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
257723, 257730, H05K 506
Patent
active
061602183
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to a housing for the accommodation of at least one electronic component, such as a chip or the like, comprising a covering layer and an opposing covering layer which accommodate the electronic component between them. The invention further relates to a process for the production of such a housing.
BACKGROUND OF THE INVENTION
For protection from unintended mechanical and chemical influences, and frequently also for the discharge and distribution of dissipated heat, it is known, in particular in association with chips, to provide these with a screening housing. This housing also offers the advantage that a terminal conductor arrangement extending outwards from the chip terminal surfaces simplifies the implementation of the following connection procedure as, by means of an outwardly fanned configuration of the terminal conductor arrangement of the housing, larger spaces can be provided between the terminal surfaces than is possible with the chip terminal surfaces.
Therefore in the currently widespread surface mounted technology (SMT) it is common practice to accommodate the chip, either alone or together with other electronic components, in a housing made of synthetic resin. In this context it is known to bond the chip onto a frame-like chip carrier and for the complete encapsulation of the chip to fill the chip carrier with a synthetic resin casting compound and enclose the chip therein.
The production of a housing of this type proves costly in practice as, due to the chip carrier's function as frame or form, its design is subject to special requirements. Furthermore the chip, and any other electronic components possibly arranged on the chip carrier, is subject to increased thermal stress when the chip carrier is filled with the synthetic resin casting compound, which not infrequently leads to damage which impairs the function of the electronic component.
OBJECT OF THE INVENTION
Therefore the object of the invention is to propose a housing for electronic components which can be produced substantially non-detrimentally to the respective electronic component(s) and to propose a process which facilitates the production of such a housing with a particularly low outlay.
This object is fulfilled by a housing having the features of claim 1 and by a process for the production of a housing having the features of claim 6.
SUMMARY OF THE INVENTION
In the housing according to the invention both the covering layer and the opposing covering layer are provided with conductor paths on their inner surfaces facing the electronic component, in such manner that the conductor paths of the covering layer connect terminal surfaces of the component to the conductor paths of the opposing covering layer, and the conductor paths of the opposing covering layer lead into outer terminals of the housing, the covering layer and/or opposing covering layer having a flexible carrier layer and being connected to one another in covering layers-connecting zones which surround the component.
Due to the flexible design of at least one covering layer, i.e. the covering layer or opposing covering layer, the electronic component can be hermetically enclosed without the need for casting with a synthetic resin or the like. This also serves to avoid the thermal stress upon the component associated with synthetic resin casting. Additionally, due to the flexible design of a least one covering layer, it is possible to provide an encasing of the component without this involving special requirements of the design of the covering layer or the opposing covering layer. The housing according to the invention also facilitates a production wherein the sealing of the housing takes place virtually in one, process step together with the establishment of the connection between the conductor paths of the covering layer to the conductor paths of the opposing covering layer.
It proves particularly advantageous if the opposing covering layer comprises at least one component-accommodating zone which is recessed relative
REFERENCES:
patent: 4941033 (1990-07-01), Kishida
patent: 5401688 (1995-03-01), Yamaji et al.
patent: 5631191 (1997-05-01), Durand et al.
Patent Abstracts of Japan, vol. 017, No. 649 (E-1468), Dec. 2, 1993 and JP, A, 05 211275, (Toshiba Corp; Others), Aug. 20, 1993.
Patent Abstracts of Japan, vol. 016, No. 415 (E-1257), Sep. 2, 1992 and JP, 4139737, (Toshiba Lighting & Technol Corp) May 13, 1992.
Patent Abstracts of Japan, vol. 012, No. 239 (E-630), Jul. 7, 1988 and JP, 3029560, (Hitachi Ltd.), Feb. 8, 1988.
Patent Abstracts of Japan, vol. 013, No. 168 (E-747), Apr. 21, 1989 and JP, A, 64 001262, (Hitachi Ltd; Others: 01), Jan. 5, 1989.
Azdasht Ghassem
Reichl Herbert
Zakel Elke
Fraunhofer-Gesellschaft zur Forderung der ange-wandten Forschung
Kincaid Kristine
Ngo Hung V
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