Chip for use with both high-speed bus and low-speed bus and...

Details Chip for use with both high-speed bus and low-speed bus and... Chip for use with both high-speed bus and low-speed bus and...

2011-02-01

2011-02-01

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07882401

ABSTRACT:
A chip for use with both a high-speed bus and a low-speed bus in a computer system includes a test control unit recorded therein a preset address data for determining a transmission path of an external signal in a test mode of the chip; an upstream control unit for transmitting the external signal to the high-speed bus in a normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode; and a downstream control unit for transmitting the external signal to the low-speed bus in the normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode.

REFERENCES:
patent: 6571357 (2003-05-01), Martin et al.
patent: 6609222 (2003-08-01), Gupta
patent: 6959257 (2005-10-01), Larky et al.
patent: 7049839 (2006-05-01), Hsiao
patent: 7143312 (2006-11-01), Wang et al.
patent: 7512024 (2009-03-01), Lee et al.
patent: 7587651 (2009-09-01), Kuo et al.
patent: 2006/0107186 (2006-05-01), Cowell et al.
patent: 2008/0115022 (2008-05-01), Su
patent: I266065 (2006-11-01), None

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