Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-15
2005-11-15
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S013000, C703S023000
Reexamination Certificate
active
06966041
ABSTRACT:
The present invention discloses a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing. The chip fabrication procedure with performance pre-testing comprising steps of: providing a chip design; determining if the chip design is correct by using a simulation environment; determining if the chip performance meets the standards by using a performance testing process; and proceeding with production of chips. The simulation method for chip testing comprises steps of: providing a simulation environment corresponding to a chip design; providing at least one set of testing commands; executing the testing commands; and calculating the time required for completing executing the testing commands. The present invention is advantageous since the time requited for product testing is reduced and so is the fabrication cost.
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Han Tony
Hsiao Chin-Fa
Wen Fu-Chu
Garbowski Leigh M.
Rosenberg , Klein & Lee
Via Technologies Inc.
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