Chip enable input buffer

Details Chip enable input buffer Chip enable input buffer

2000-09-14

2001-08-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S226000

Reexamination Certificate

active

06275421

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and, more particularly, to a method and system for providing input voltage buffering in a flash electrically erasable programmable memory (“EEPROM”).
BACKGROUND OF THE INVENTION
Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory is used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. Some applications require retention of the instructions and/or data in a permanent or non-volatile storage medium. Such memories maintain information when the device is turned off or power is removed. Exemplary applications include computer Basic Input Output Systems (BIOS) storage and diskless handheld computing devices, such as personal digital assistants.
Flash memories store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating gate transistors in a silicon substrate to form a core cell area. A floating gate transistor is capable of storing electrical charge on a separate gate electrode, known as a floating gate, that is separated by a dielectric layer from a control gate electrode. Generally, stored electrical charge in the floating gate represents a data state.
Flash memory devices also include a periphery area in the silicon substrate. Logic and addressing functions are performed by a plurality of logic and addressing circuits in the periphery area. The logic and addressing circuits perform internal logic operations such as reading, programming and erasing the stored charge in the floating gate transistors.
Flash memory devices also use a supply voltage (Vcc). The supply voltage (Vcc) is generated by a fixed voltage power supply that is used to power the internal logic operations.
The flash memory is electrically interfaced with a system processor of an electronic system or device. When the operation of the flash memory is desired by the electronic system or device, the flash memory is selected with a chip enable signal. When selected by the typically logic low (logic “0”) chip enable signal, the flash memory's logic and addressing circuitry is activated such that the flash memory can be operated by the electronic system or device.
When the flash memory is deselected by the chip enable signal that is typically logic high (logic “1”), it is in a standby mode. The standby mode decreases the power consumption of the flash memory because less of the logic and addressing circuitry is activated. It is desirable to have a low standby current draw to maintain the lowest possible power consumption of the flash memory during standby mode.
Typically, the supply voltage (Vcc) originates from the same supply voltage that powers the electronic system or device. As such, the chip enable signal is generated by the electronic system or device using the supply voltage (Vcc). In some cases, the electronic system or device is powered from another power supply source that is used to generate the chip enable signal.
A problem occurs when the electronic system generates the chip enable signal at voltage levels that are lower than the supply voltage (Vcc). When the voltage level of the chip enable signal that is logic high is less than the supply voltage (Vcc), the logic circuit within the flash memory that receives the chip enable signal may not operate properly. Since the logic circuit is operated with the supply voltage (Vcc), the chip enable signal used to deselect the flash memory may not be capable of completely deactivating the logic circuit. As such, when the flash memory is deselected and enters the standby mode, leakage current may occur that increases the standby current and the flash memory will consume more power.
SUMMARY
The presently preferred embodiments are capable of being placed in a standby mode by a logic high chip enable signal with a voltage level that is less than the magnitude of the supply voltage (Vcc) without causing increased standby current. In addition, the presently preferred embodiments maintain the standby current at desirably low levels when the external supply voltage is greater than the supply voltage (Vcc).
The present invention discloses a memory device that is operable with a supply voltage (Vcc). In the presently preferred embodiment, the memory device is a flash memory. The flash memory is controlled with electric signals generated with an external supply voltage by an electronic system. The flash memory comprises a plurality of logic circuits that are electrically connected with the supply voltage (Vcc). In addition, the flash memory includes an external voltage buffer circuit.
The presently preferred external voltage buffer circuit includes a clamping circuit and an activation circuit. The clamping circuit is electrically connected with the supply voltage (Vcc), the external supply voltage and the activation circuit. The activation circuit is electrically connected with the electronic system and the logic circuits. The clamping circuit generates a clamped signal that is received by the activation circuit. The activation circuit receives the clamped signal and generates an output signal when activated by the electric signals. The output signal controls activation of the logic circuits.
Another embodiment of the present invention discloses a method of buffering electric signals with a memory device. The method comprises the acts of providing a supply voltage (Vcc) and an external supply voltage that are received by a clamping circuit. The clamping circuit generates a clamped signal with the supply voltage (Vcc) and the external supply voltage. The clamped signal is received by an activation circuit. Electric signals are generated with the external supply voltage to direct the activation circuit to generate an output signal.
Power consumption of the flash memory during the standby mode is maintained at desirably low levels by deactivating the activation circuit with the electric signal that is the logic high chip enable signal. The activation circuit is deactivated since it operates with the voltage level of the clamped signal. The voltage level of the clamped signal is controlled to be about equal to the supply voltage (Vcc) or the external supply voltage. Since the difference in the voltage level of the logic high chip enable signal and the operating voltage level of the activation circuit is controlled, low levels of standby current during the standby mode are maintained to keep power consumption at desirable low levels.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.


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patent: 5500614 (1996-03-01), Egawa
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patent: 5699301 (1997-12-01), Egawa
patent: 5822257 (1998-10-01), Ogawa
patent: 5877989 (1999-03-01), Egawa

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