Chip enable control circuit, memory control circuit, and...

Details Chip enable control circuit, memory control circuit, and... Chip enable control circuit, memory control circuit, and...

2007-09-11

2007-09-11

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S227000, C365S189090, C365S194000, C365S189070

Reexamination Certificate

active

11378391

ABSTRACT:
A CE control circuit includes a CE signal generating circuit which sets a CE signal to an enable level when bringing the memory to an operable state or sets the CE signal to a disable level when bringing the memory to a low power consumption state, and a reference value generating circuit which outputs a reference value corresponding to a period during which the memory is allowed to be continuously in the operable state, wherein when not receiving a startup request signal of the memory for a period during which the CE signal is the enable level, the CE signal generating circuit elongates the period during which the CE signal is the enable level to a period corresponding to the reference value and which is not shorter than a CE enable signal hold time of the memory, and sets the CE signal to the disable level after the elongated period passes.

REFERENCES:
patent: 5134586 (1992-07-01), Steele
patent: 5303181 (1994-04-01), Stockton
patent: 5349565 (1994-09-01), Wu et al.
patent: 5422855 (1995-06-01), Eslick et al.
patent: 5798980 (1998-08-01), McClure
patent: 6009494 (1999-12-01), Pawlowski
patent: 7224623 (2007-05-01), Partsch et al.
patent: 08-076875 (1996-03-01), None

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