Chip design with power rails under transistors

Details Chip design with power rails under transistors Chip design with power rails under transistors

2001-11-16

2003-06-24

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S276000

Reexamination Certificate

active

06583045

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to the structure and fabrication of semiconductor devices and more particularly to the placement of power rails (VSS/VDD) under transistors.
2) Description of the Prior Art
For IC designs using standard cells, Place & Route is a very important step in the design flow to determine the actual layout of the final design. The methodology supported by today's EDA tools is as following.
The standard cells are placed abutted in rows where the power rails (VDD, VSS) feeding the cells goes horizontally on the upper and lower side of the cells.
To keep the IR drop under some certain levels and to conform to the EM (Electro Migration) rules, a power mesh must be routed above the standard cells which provides the standard cell VDD/VSS power rails with power at equally distributed distance. The distance between each feed-point as well as the number of VIAs that must be dropped is dependent of the consumed power and the line width of the power rail. There are also alternatives concerning in which metal layers to route the power mesh. Usually two different layers are used, one for the horizontal routing and one for the vertical routing of the power mesh.
The disadvantages of the current method of placing VDD/VSS power rails in the metal layers over the transistors on the front side of the chip. If lower metal layers are chosen, such as M
1
and M
2
, then empty space between the standard cells where the mesh will be routed, must be reserved on the cost of bigger chip area. This solution is rarely used today. On the other hand, if higher metal layers are chosen, then the stacked VIA's that must be dropped on every feed-point will occupy valuable routing resource on the underlying routing layers. The underlying layers where signals are to be routed will be restricted by the big number of stacked VIA's dropped from the power mesh located at above layers. In summary, the VDD/VSS nets are the only net that must be connected to ALL standard cells and therefore stealing a lot of routing resources from the signal nets.
Another concern is that power routing and signal routing have conflicting requirements on the process characteristics. Signals are switching nets, which requires low Capacitance to achieve low signal delay. Power lines on the contrary are constant and require low Resistance to achieve low IR-drop. From process point of view, low R usually means thicker (deeper) metal layers on the cost of higher C parasitic, while low C means thinner metal layers with higher R as a result. In many processes today the requirements set by Signal routing is dominating (low C, high R). Therefore, the problem of IR-drop and EM on the power lines still remains an increasing problem.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,811,237 (Putatunda et al.) Structured Design Method for Generating a Mesh Power Bus Structure in High Density Layout of VLSI Chips; U.S. Pat. No. 5,404,310 (Mitsuhashi) Method and Apparatus for Power-Source Wiring Design of Semiconductor Integrated Circuits; U.S. Pat. No. 6,060,748 (Uchida et al.) Semiconductor Integrated Circuit Device Using a Silicon-Oninsulator Substrate and U.S. Pat. No. 5,936,282 (Baba.et al.) Semiconductor Device having Input Protection Circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating power rails on the backside of a chip.
It is an object of the present invention to provide an inverter with power rails under the transistors.
The present invention provides a device and a method of manufacturing an integrated circuit with power rails under transistors.
In a preferred embodiment, power rails are formed over a substrate. Then devices, such as transistors, are formed over the power rails. Signal lines can be formed over the devices. A preferred device is an inverter. A preferred embodiment comprises forming a first power rail (e.g., VSS) over a substrate. Then we form a second power rail (e.g., VDD) over the first power rail. The second power rail is insulated from the first power rail. Next,.transistors or other devices are formed over the first and the second power rails.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 5404310 (1995-04-01), Mitsuhashi
patent: 5936282 (1999-08-01), Baba et al.
patent: 6060748 (2000-05-01), Uchida et al.
patent: 6355950 (2002-03-01), Livengood et al.

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