Chip design verifying and chip testing apparatus and method

Details Chip design verifying and chip testing apparatus and method Chip design verifying and chip testing apparatus and method

2007-01-03

2009-08-04

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

07571400

ABSTRACT:
A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, and having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.

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Translation of Office Action as issued by German Patent and Trademark Office; Jan. 14, 2008. All references cited in the foreign Office action and not previously submitted are listed above.

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