Chip design method for designing integrated circuit chips...

Details Chip design method for designing integrated circuit chips... Chip design method for designing integrated circuit chips...

2002-05-22

2004-08-10

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C714S718000, C714S727000, C714S733000, C714S734000

Reexamination Certificate

active

06775811

ABSTRACT:

REFERENCE TO COMPUTER PROGRAM LISTING APPENDIX
The following computer program listing files are submitted on a compact disc and are incorporated herein by reference:
NAME CREATION DATE SIZE (bytes)
AppendixI.txt Aug. 28, 2002 9,773
AppendixII.txt Aug. 28, 2002 10,515
AppendixIII.txt Aug. 28, 2002 835
AppendixIV.txt Aug. 28, 2002 2,147
AppendixV.txt Aug. 28, 2002 15,719
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to integrated circuit chips and more particularly to integrated circuit chips including embedded memories.
2. Background Description
Increasingly, integrated circuit chips include embedded memories. Application specific integrated circuits (ASICs) in particular have become more and more complex and, correspondingly, more and more frequently include embedded memory. As technology has advanced and feature size has shrunk, embedded memory granularity (density) has increased. In this trend towards more complex logic on an ASIC with a larger embedded memory both, is driven by and, is driving the effort to integrate a system on a chip (SOC).
Testing an embedded memory on a complex logic chip is a well known problem. Thus, self test logic has been developed for inclusion on the chip to test the embedded memory and is known as built-in self-test (BIST) logic. There are logic tools that are currently available, such as from LogicVision, Inc., which are specifically designed for creating BIST for embedded memories. These logic tools generate a well defined test logic architecture that may be wrapped around an embedded memory. Typically, the embedded memory and the BIST logic are defined with and included in the ASIC logic.
Once ASIC logic is defined, typically, the top level chip definition or the chip footprint is partitioned and space is designated for specific functions. After this partitioning, the square/rectangular chip footprint with areas boxed off for specific functions resembles the floorplan of a building or house. So, this partitioning step is commonly referred to as floorplanning. Likewise other terms normally associated with Realty are used occasionally for chip design. Floorplanning is a very important step of chip design.
If a chip is improperly floorplanned such that insufficient space is allocated for a particular function, it may be necessary to locate part of that function elsewhere on the chip, which would introduce otherwise unanticipated delays. Normally, the ASIC designer attempts to take into account any delays that might be added during placement and wiring. Unfortunately, delay added by splitting a macro or, when associated logic is placed a significant distance from the macro, can blow the designer's timing budgets and may require significant additional post placement analysis and redesign to recover, if recovery is possible at all.
Delays may be added to embedded memory timing from locating BIST logic at some distance to the memory, such that loads on the particular embedded memory are increased, slowing it, i.e., significantly degrading performance. Also, even if the embedded memory performance is not degraded, splitting the BIST logic can give apparent performance times that are much higher than the actual embedded memory performance. In this case even though the embedded memory performs satisfactorily, delays in the BIST logic may necessitate additional design time to improve performance on a memory that, in actuality, is performing satisfactorily.
Thus, there is a need for a way to insure automatically that BIST logic is placed as close as possible to the embedded memories that the logic is intended to test, to minimize any added delay or to avoid any apparent delay that must be separated from the BIST to adequately test the embedded memories.
SUMMARY OF THE INVENTION
It is a purpose of the invention to facilitate testing embedded memories;
It is another purpose of the invention to insure placement of memory self test logic close to the embedded memory that it is testing.
The present invention is a method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.


REFERENCES:
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 6370677 (2002-04-01), Carruthers et al.
patent: 6456961 (2002-09-01), Patil et al.
patent: 6564305 (2003-05-01), Moore
patent: 2003/0115564 (2003-06-01), Chang et al.

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