Chip core size estimation

Details Chip core size estimation Chip core size estimation

2001-04-18

2003-02-25

Nelms, David (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06526553

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to estimation of the minimal chip core size, which is useful in designing integrated circuit (IC) chips to successfully place cells and route wires defined by a given gate level netlist in a given technology library.
BACKGROUND OF THE INVENTION
In order to successfully layout cells and route conductive paths (wires) in an integrated circuit chip, it is important to estimate the approximate size of the chip core. Presently, chip size is estimated on the skill and experience of the IC chip designer. Persons with less skill often need to calculate the approximate size of the chip, a process that is quite laborious. Errors in chip size estimates can affect the placement and routing of conductive wires in the chip, requiring redesign of the entire chip. There is, accordingly, a need for an automated process for accurately estimating the chip core size for purposes of placement and layout.
SUMMARY OF THE INVENTION
A minimum core size of an integrated circuit chip is estimated based on parameters of the technology used for placing cells and routing conductive paths on the chip, and the chip netlist. An average wire length is calculated for the nets of the netlist based on the perimeter of the net and of the core. The center of each cell is assigned x,y coordinates to minimize the average wire length. The widths of routing channels between consecutive columns and associated core sizes are estimated based on the estimated cell placement and the technology parameters. The estimated minimum core size is identified.
The average wire length is calculated from the average size of the half-perimeters of the nets, and dividing that average by the half-perimeter of the core.
The cell placement is performed by assigning the center of each cell to initial x,y coordinates. The center of each net is calculated, and new coordinates are calculated for each cell center based on the prior x,y coordinates for that cell, as well as the x,y coordinates of the centers of each net connected to the cell and the numbers of pins of those nets. The cells are then spread over the x and y extents of the net. The cell placement steps are preferably repeated through plural iterations.
In preferred embodiments, the estimated minimum core size is adjusted for the area required for clock buffers and megacells.
Another aspect of the present invention is the provision of computer readable program that is embedded in a computer usable medium. The computer readable program includes program code that causes a computer to estimate a minimum core size and carry out the process of the invention.


REFERENCES:
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patent: 5563801 (1996-10-01), Lee et al.
patent: 6249902 (2001-06-01), Igusa et al.
patent: 6301693 (2001-10-01), Naylor et al.
patent: 6327494 (2001-12-01), Kanazawa

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