Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-10-23
2004-04-06
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S700000, C257S758000, C257S737000, C174S050510, C174S261000
Reexamination Certificate
active
06717255
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a chip carrier and an electronic package for a high-frequency electronic device.
BACKGROUND OF THE INVENTION
Several types of electronic devices utilizing a circuit, which is integrated in a chip of semiconductor material, are possible. The chip is typically mounted on a chip carrier, so as to protect the chip from mechanical stresses, and is then encapsulated to produce an electronic package. The chip carrier includes an insulating substrate with conductive tracks, each track bonded to a corresponding terminal of the chip. Each track terminates at a contact pad (typically for connection to a printed circuit board).
The transmission of a signal in a corresponding conductive track generates an electromagnetic wave; the wave propagates along a transmission line defined by the conductive track and an underlying ground plane (which is connected to a reference voltage for shielding the conductive track from electromagnetic interference). When the chip operates at a high frequency (for example more than about 1 Gigahertz), the propagation of the wave (microwave) can severely affect the performance of the electronic package.
Particularly, any discontinuity (or transition) in the transmission line that the signal encounters as it travels along a conductive track, such as any change in structure, material properties and/or design features, generates a reflected wave. Moreover, the package includes stray structures (capacitors, inductors and resistors), which act as low pass filters for the transmitted signal. As a consequence, the integrity of the electromagnetic wave propagated along the transmission line degrades, especially at high frequencies.
The transmitted signal, switching between a low voltage (logic value 0) and a high voltage (logic value 1) generates a square-shaped wave. Because of discontinuities in the transmission line, this wave is generally received as a pseudo-sinusoidal wave. The quality of the transmitted wave can be visualized by a so-called “eye diagram”, which plots the value of the received signal as a function of the phase of a clock signal controlling the electronic package. The above described discontinuities in the transmission line reduce the central opening of the eye diagram. Therefore, it is quite difficult to understand if a switching transition has actually taken place or if the shift of a signal baseline is due to background noise.
These drawbacks are particular acute in modern electronic devices working with a reduced level of power supply voltage (down to 1.2 V). In this case, there is a very low margin to discriminate between the logic value 0 (1V) and the logic value 1 (1.2V).
Moreover, the continuous trend towards miniaturization of electronic devices requires a reduction in the dimensions of chip carrier conductive tracks on which such devices are packaged. However, the impedance of the transmission line must be maintained at a desired value which optimizes the performance of the electronic device (typically 50 W). Therefore, it is necessary to use a thin dielectric layer between the conductive tracks and the ground plane of the electronic package (since the impedance is inversely proportional to the track width and directly proportional to the dielectric layer thickness). A shortened distance between conductive tracks and the ground plane increases the value of a corresponding stray capacitance. As a consequence, the bandwidth of the transmission line is strongly reduced.
Therefore, as the quality of the transmission in the package is degraded it can cause the electronic device to operate at a frequency far lower than the working frequency which is afforded by the chip.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the above mentioned drawbacks.
According to one aspect of the invention, there is provided a chip carrier comprising a first conductive layer having at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal, and a reference structure including a first conductive reference track insulated and spaced from the first conductive layer, the first conductive reference track having a first portion and a second portion spacedly positioned from the first portion, and a second conductive reference track insulated from the first conductive layer and the first conductive reference track, a portion of the second conductive reference track spaced between the first conductive layer and the first conductive reference track, the signal track substantially overlying the portion of the second conductive reference track, and the contact area substantially overlying the first portion of the first conductive reference track, the signal track being electrically shielded by the reference structure.
According to another aspect of the invention, there is provided an electronic package comprising a chip carrier including a first conductive layer having at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal, the chip carrier further including a reference structure including a first conductive reference track insulated and spaced from the first conductive layer, the first conductive reference track having a first portion and a second portion spacedly positioned from the first portion, and a second conductive reference track insulated from the first conductive layer and the first conductive reference track, a portion of the second conductive reference track spaced between the first conductive layer and the first conductive reference track, the signal track substantially overlying the portion of the second conductive reference track, and the contact area substantially overlying the first portion of the first conductive reference track, the signal track being electrically shielded by the reference structure, and a semiconductor chip positioned on the chip carrier and having at least one terminal electrically interconnected to the at least one contact area.
The above objects, advantages, and features of the present invention will become more readily apparent from the following detailed description of the presently preferred embodiments as illustrated in the accompanying drawings.
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Oggioni Stefano
Ravanelli Roberto
Cruz Lourdes
Cuneo Kamand
Hogg William N.
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