Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-04-02
2003-11-04
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S755090
Reexamination Certificate
active
06642727
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a chip carrier arrangement for manufacturing a chip module for an encased chip arrangement with a chip carrier, which has a conductor path structure on a chip contact side with through connections extending to an outer contact side of the chip carrier, wherein these through connections are allocated to terminal faces of at least one chip, and used to establish component contacts on the outer contact side of the chip carrier. In addition, this invention relates to a method for manufacturing a chip carrier arrangement for a chip module.
BACKGROUND OF THE INVENTION
A known method for more easily contacting chips on substrates, serving as the basis for building electronic assemblies, is to provide chips with so-called “rewindings”. These enable an array of terminal faces uniformly distributed on the surface of the chip. This is based on a peripheral terminal face arrangement, with an enlarged spacing between terminal faces to simplify contacting with the substrate or other components. As a rule, such a rewinding is implemented by contacting the chip on a carrier material provided with the corresponding conductor path structure. Chip carrier arrangements formed out of the chip and carrier material in this way are subsequently at least partially encased by a plastic material to make the chip carrier arrangement easier to handle and increase the operational safety, resulting in so-called “chip size-packages”.
It is also known to subject chip carrier arrangements, of the kind described above, to an electrical component test prior to fabricating the chip casing. This allows a quality assurance to be performed before completion of the chip packages by checking the contact between the carrier material and chip or the functionality of the chip. Such tests performed under temperature load are also called “burn-in tests”.
In known chip carrier arrangements, the carrier material usually taking the form of a carrier film and provided with a conductor path structure, is therefore furnished with test contacts. This is in addition to through connections necessary for establishing the terminal face array with component contacts on the outer contact side of the carrier material. The test contacts are designed differently from the through connections and arranged on the chip contact side. This yields an arrangement of component contacts opposite each other on the outer contact side of the carrier material and test contacts on the chip contact side of the carrier material. Based on the fact that the chip carrier arrangement or chip package is handled, both for contacting the chip carrier arrangement with a testing device for performing component tests and contacting the chip carrier arrangement or chipsize package with a substrate, the opposed arrangement of test contacts and component contacts hence results in varying feed directions for the chip carrier arrangement or chipsize package in the different contacting processes.
SUMMARY AND OBJECTS OF THE INVENTION
The object of this invention is to provide a chip carrier arrangement or a method for manufacturing a chip carrier arrangement that enables the simplified fabrication of chip modules or chipsize packages, which are subjected to a component test during manufacture.
According to the invention, a chip carrier arrangement is provided for manufacturing a chip module for an encased chip arrangement with a chip carrier, whose one chip contact side exhibits a conductor path structure with through connections extending to an outer contact side of the chip carrier, wherein these through connections are allocated to terminal faces of at least one chip, and are used to form component contacts on the outer contact side of the chip carrier.
In the chip carrier arrangement according to the invention, the chip carrier, in addition to the through connections for establishing the component contacts on the outer contact side, has other through connections connected with the conductor path structure to establish test contacts on the outer contact side used for contacting with test connections of a test board.
Therefore, the chip carrier arrangement according to the invention makes it possible to arrange both the component contacts and the test contacts on the outer contact side of the chip carrier. This makes it possible to both contact the chip carrier arrangement with a test board for performing an electrical component test, and contact the chip carrier arrangement or contact the chipsize package subsequently formed out of the chip carrier arrangement in the same contacting direction, e.g., uniformly via the face-down method.
If the terminal faces of the chip are connected with the conductor path structure or through connections of the chip carrier via elevated contact metallizations in order to form the chip carrier arrangement, i.e., for electrically contacting the chip with the chip carrier, it is possible not just to contact the chip carrier arrangement with the test board or contact the chipsize package with the substrate using the face-down method, but already to contact the chip with the chip contact side of the chip carrier. As a result, all necessary contacting processes can be performed based on a uniform method.
If the through connections forming the test contacts are provided with elevated contact metallizations on the outer contact side of the chip carrier in order to electrically contact the chip carrier with the test board, contacting for subsequent performance of the component test can be executed without any preceding preparation of the contact connections of the test board with connecting material.
It is extremely advantageous if both the contact metallizations of the component contacts and the contact metallizations of the test contacts are formed in the same manner and/or out of the same connecting material, since the uniform use of connecting material or uniform manner of applying the connecting material reduces the production costs.
In this connection, it is particularly advantageous if all contact metallizations consist of solder balls, which can be easily applied to the corresponding contact points without any preparatory measures, e.g., the application of a soldering material mask on the chip carrier.
The method according to the invention enables the particularly simple manufacture of a chip carrier arrangement used to fabricate a chip module for a chipsize package, and a particularly easy integration of a component test into the manufacturing process. According to the invention, the method involves the following steps:
contacting a chip on a chip contact side of a chip carrier provided with a conductor path structure in such a way as to establish an electrical contact between the terminal faces of the chip and with the through connections of the chip carrier connected with the conductor path structure;
contacting the chip carrier on a test board provided with test connections in such a way as to establish an electrical contact between the through connections of the chip carrier and test connections of the test board on the outer contact side of the chip carrier; and
separating out a chip carrier section of the chip carrier connected with the chip via the contact metallizations in order to form a chip module independent of a residual chip carrier remaining on the test board.
The method according to the invention makes it possible to both contact the chip with the chip carrier and contact the chip carrier with the test board using one and the same method or one and the same device, so as to enable the formation of a chip module independent of the residual chip carrier by separating out a part of the chip carrier connected with the chip after the contacting processes. After removal of the residual chip carrier, the test board can be reused.
In an especially advantageous manner, the method according to the to invention offers the possibility of performing two optional procedures, wherein the first option involves first contacting the chip on the chip carrier and then contacting the chip ca
Rohde Hartmut
Wendland Gerhild
Karlsen Ernest
McGlew and Tuttle , P.C.
Pac Tech-Packaging Technologies GmbH
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