Chip capacitance measurement circuit

Details Chip capacitance measurement circuit Chip capacitance measurement circuit

2000-08-02

2002-06-11

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S519000, C324S762010

Reexamination Certificate

active

06404222

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89111584, filed Jun. 14, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a capacitance measurement circuit. More particularly, the present invention relates to a measurement circuit for measuring the capacitance of a metallic parasitic capacitor on a silicon chip.
2. Description of Related Art
In semiconductor fabrication, metallic interconnects are often used to link up various devices. Due to the coupling between a metallic interconnect and a substrate or between pairs of metallic interconnects, metallic parasitic capacitance are formed. Since the response of a transistor is often delayed by the presence of metallic parasitic capacitance, the magnitude of the parasitic capacitance is preferably measured in advance so that its overall effect on chip performance can be accessed.
Parasitic capacitance can be directly measured by a high-precision capacitor meter. However, direct measurement of capacitance by a capacitor meter is feasible only for the measurement of capacitance in the pico-farad (PF) range (that is, 10
−12
Farad). Due to rapid progress in semiconductor manufacturing technologies, the width of metallic interconnects continues to shrink to a smaller dimension. Hence, magnitude of the metallic parasitic capacitance in a silicon chip correspondingly decreases to the femto-farad (FF) range (that is, 10
−15
Farad). For such a small capacitance, the value of parasitic capacitance can no longer be accurately measured by a capacitor meter.
The conventional method of measuring a low capacitance value includes the use of a charge-based capacitance measurement (CBCM) circuit.
FIG. 1
is a schematic circuit diagram of a conventional CBCM circuit. The capacitance measurement circuit actually comprises of two pairs of symmetrical and matching MOS transistor circuits. One transistor circuit includes a pair of PMOS transistors
106
and
110
while the other transistor circuit includes a pair of NMOS transistors
108
and
112
.
As shown in
FIG. 1
, a current meter
102
is serially connected between a power supply
100
and PMOS transistor
106
on the left side of the capacitance measurement circuit. Current meter
102
measures the current flowing from power source
100
to the source terminal of PMOS transistor
106
. Another current meter
104
on the right side of the capacitance measurement circuit is serially connected to power source
100
and PMOS transistor
110
. Similarly, current meter
104
measures the current flowing from power source
100
to the source terminal of PMOS transistor
110
.
On the left side, the drain terminal of PMOS transistor
106
and the drain terminal of NMOS transistor
108
are connected in parallel with a m
1
metal strip
114
. Assume that the parasitic capacitor formed between metal strip
114
and the substrate has a capacitance C
wire
. Similarly on the right side, the drain terminal of PMOS transistor
110
and the drain terminal of NMOS transistor
112
are connected in parallel with a m
1
metal strip
116
. Assume the parasitic capacitor that is formed from m
1
metal strip
116
and a m
2
metal strip
118
has a capacitance of C
x
and the parasitic capacitor that forms from m
1
metal strip
116
and the substrate has a capacitance C
wire
. Metal strip
118
is connected to the ground. In addition, m
1
metal strip
114
and m
1
metal strip
116
are symmetrical to each other. With such a configuration, the metallic parasitic capacitance measured via the drain terminal of PMOS transistor
110
should be C
wire
+C
x
.
The gate terminal of PMOS transistor
106
and the gate terminal of PMOS transistor
110
are connected in parallel to the output terminal V
1
of a signal generator
120
. The gate terminal of NMOS transistor
108
and the gate terminal of NMOS transistor
112
are connected in parallel to another output terminal V
2
of signal generator
120
. The source terminal of NMOS transistor
108
and the source terminal of NMOS transistor
112
are connected in parallel to the ground.
FIG. 2
is a timing diagram showing the signals needed for a conventional CBCM circuit during operation. As shown in
FIG. 2
, control signals needed for the CBCM circuit are generated by signal generator
120
. Signal generator
120
issues control signals V
1
to the gate terminal of PMOS transistor
106
and the gate terminal of PMOS transistor
110
. Signal generator
120
also issues control signals V
2
to the gate terminal of NMOS transistor
108
and the gate terminal of NMOS transistor
112
. Ideally, a conventional CBCM circuit should operate in steps according to the timing diagram in FIG.
2
. The steps includes:
Step one: During time interval t
0
-t
1
, all MOS transistors are in the shut-off state, and both current meters
102
and
104
register a zero current;
Step two: During time interval time t
1
-t
2
, PMOS transistor
106
and PMOS transistor
110
are in a conductive state while NMOS transistor
108
and NMOS transistor
112
are in a shut-off state. During this period, capacitor C
wire
(that is, m
1
metal strip
114
) and capacitor C
wire
+C
x
(that is, m
1
metal strip
116
and m
2
metal strip
118
) are charged. Consequently, currents of different values pass through the respective current meters
102
and
104
;
Step three: During time interval t
2
-t
3
, all MOS transistors are in the shut-off state, and both current meters
102
and
104
register a zero current;
Step four: During time interval t
3
-t
4
, both PMOS transistors
106
and
110
are in a shut-off state while both NMOS transistors
108
and
112
are in a conductive state. During this period, capacitor C
wire
(that is, m
1
metal strip
114
) and capacitor C
wire
+C
x
(that is, m
1
metal strip
116
and m
2
metal strip
118
) are discharged.
In the aforementioned four steps, the average current flowing through current meter
102
is I
wire
and the average current flowing through current meter
104
is I
wire+x
.
The value of capacitance C
x
can be deduced using the following formulae:
I
wire+x
=(
C
wire
+C
x
)·
Vdd·f;
I
wire
=C
wire
·Vdd·f;
C
x
=
I
wire
+
x
-
I
wire
Vdd
·
f
,
where f is the frequency (as shown in FIG.
2
).
In practice, at time t
2
, PMOS transistor
106
and PMOS transistor
110
begin to change from a conductive state to a shut-off state while NMOS transistor
108
and NMOS transistor
112
are in a shut-off state. An equivalent capacitance between the source terminal and the gate terminal of PMOS transistor
106
can be obtained by looking up the gate terminal of PMOS transistor
106
. Similarly, an equivalent capacitance between the source terminal and the gate terminal of PMOS transistor
106
and the capacitor C
wire
can be obtained by looking down the gate terminal of PMOS transistor
106
. Similarly, an equivalent capacitance between the source terminal and the gate terminal of PMOS transistor
110
can be obtained by looking up the gate terminal of PMOS transistor
110
. An equivalent capacitance between the source terminal and the gate terminal of PMOS transistor
110
and the capacitor C
wire
+C
x
can be obtained by looking down the gate terminal of PMOS transistor
110
.
FIG. 3
is a graph showing the time trace of negative current produced by a conventional CBCM circuit through a SPICE simulation. At time t
2
(control signal V
1
304
changes from a ground voltage to a voltage Vdd as shown in FIG.
3
), a negative current i
wire
returns from the gate terminal of PMOS transistor
106
to current meter
102
and a negative current I
wire+x
returns from the gate terminal of PMOS
110
to current meter
103
. As shown in
FIG. 3
, negative current i
wire
302
differs from negative current I
wire+x
300
because capacitance looking into the lower portion from the gate terminal of PMOS transistor
110
is greater than the capacitance looking into the lower portion from th

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