Chip bond layout for chip carrier for flip chip applications

Details Chip bond layout for chip carrier for flip chip applications Chip bond layout for chip carrier for flip chip applications

2007-09-18

2007-09-18

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S781000, C257S774000, C257SE21503, C257SE21511

Reexamination Certificate

active

11135720

ABSTRACT:
A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a predefined chip size and a predefined carrier technology.

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