Chip assembly including package element and integrated...

Details Chip assembly including package element and integrated... Chip assembly including package element and integrated...

2007-05-30

2010-06-15

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

C257SE29324, C257SE21505, C257S737000, C257S738000, C257S698000, C257S734000, C257S772000, C257S782000

Reexamination Certificate

active

07737513

ABSTRACT:
The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.

REFERENCES:
patent: 6566170 (2003-05-01), Marion et al.
patent: 6605828 (2003-08-01), Schwarzrock et al.
patent: 6646289 (2003-11-01), Badehi et al.
patent: 6661084 (2003-12-01), Peterson et al.
patent: 6777767 (2004-08-01), Badehi et al.
patent: 2002/0000649 (2002-01-01), Tilmans et al.
patent: 2002/0160583 (2002-10-01), Song
patent: 2004/0188782 (2004-09-01), Fujii
patent: 2008/0311704 (2008-12-01), Oberle
patent: 1513100 (2005-03-01), None
patent: 2006-747750 (2006-03-01), None

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